Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2550119	1			T1	1		T2	1		T3	1
all_pins[1]	2550119	1			T1	1		T2	1		T3	1
all_pins[2]	2550119	1			T1	1		T2	1		T3	1
all_pins[3]	2550119	1			T1	1		T2	1		T3	1
all_pins[4]	2550119	1			T1	1		T2	1		T3	1
all_pins[5]	2550119	1			T1	1		T2	1		T3	1
all_pins[6]	2550119	1			T1	1		T2	1		T3	1
all_pins[7]	2550119	1			T1	1		T2	1		T3	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	20343889	1			T1	8		T2	8		T3	8
values[0x1]	57063	1			T25	32		T35	4		T37	87
transitions[0x0=>0x1]	56034	1			T25	23		T35	4		T37	40
transitions[0x1=>0x0]	56053	1			T25	23		T35	4		T37	40

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2549842	1			T1	1		T2	1		T3	1
all_pins[0]	values[0x1]	277	1			T25	5		T37	24		T38	4
all_pins[0]	transitions[0x0=>0x1]	202	1			T25	3		T37	1		T38	3
all_pins[0]	transitions[0x1=>0x0]	328	1			T25	2		T37	3		T38	2
all_pins[1]	values[0x0]	2549716	1			T1	1		T2	1		T3	1
all_pins[1]	values[0x1]	403	1			T25	4		T37	26		T38	3
all_pins[1]	transitions[0x0=>0x1]	287	1			T25	4		T37	4		T38	1
all_pins[1]	transitions[0x1=>0x0]	236	1			T25	1		T35	1		T37	2
all_pins[2]	values[0x0]	2549767	1			T1	1		T2	1		T3	1
all_pins[2]	values[0x1]	352	1			T25	1		T35	1		T37	24
all_pins[2]	transitions[0x0=>0x1]	309	1			T25	1		T35	1		T37	24
all_pins[2]	transitions[0x1=>0x0]	148	1			T25	5		T37	1		T38	1
all_pins[3]	values[0x0]	2549928	1			T1	1		T2	1		T3	1
all_pins[3]	values[0x1]	191	1			T25	5		T37	1		T38	4
all_pins[3]	transitions[0x0=>0x1]	139	1			T25	4		T37	1		T38	3
all_pins[3]	transitions[0x1=>0x0]	161	1			T25	4		T37	4		T38	5
all_pins[4]	values[0x0]	2549906	1			T1	1		T2	1		T3	1
all_pins[4]	values[0x1]	213	1			T25	5		T37	4		T38	6
all_pins[4]	transitions[0x0=>0x1]	170	1			T25	2		T37	4		T38	5
all_pins[4]	transitions[0x1=>0x0]	1971	1			T25	1		T35	1		T37	3
all_pins[5]	values[0x0]	2548105	1			T1	1		T2	1		T3	1
all_pins[5]	values[0x1]	2014	1			T25	4		T35	1		T37	3
all_pins[5]	transitions[0x0=>0x1]	1434	1			T25	4		T35	1		T37	3
all_pins[5]	transitions[0x1=>0x0]	52833	1			T25	3		T37	2		T38	4
all_pins[6]	values[0x0]	2496706	1			T1	1		T2	1		T3	1
all_pins[6]	values[0x1]	53413	1			T25	3		T37	2		T38	4
all_pins[6]	transitions[0x0=>0x1]	53357	1			T25	2		T37	1		T38	3
all_pins[6]	transitions[0x1=>0x0]	144	1			T25	4		T35	2		T37	2
all_pins[7]	values[0x0]	2549919	1			T1	1		T2	1		T3	1
all_pins[7]	values[0x1]	200	1			T25	5		T35	2		T37	3
all_pins[7]	transitions[0x0=>0x1]	136	1			T25	3		T35	2		T37	2
all_pins[7]	transitions[0x1=>0x0]	232	1			T25	3		T37	23		T38	4