Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16554

1

T16

10

T17

2

T21

87

auto[1]

12172

1

T13

14

T16

10

T53

10

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3423	1			T22	10		T53	10		T64	26
values[1]	3541	1			T13	14		T17	2		T55	84
values[2]	4366	1			T63	8		T58	20		T279	6
values[3]	3481	1			T16	20		T21	87		T57	16
values[4]	3857	1			T216	6		T62	77		T58	21
values[5]	3424	1			T24	8		T56	8		T125	6
values[6]	3290	1			T94	8		T61	24		T58	25
values[7]	3344	1			T275	22		T37	31		T280	2

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3980	1			T22	10		T209	4		T60	14
values[1]	3565	1			T61	24		T90	22		T231	22
values[2]	3645	1			T24	8		T179	8		T216	6
values[3]	3335	1			T17	2		T53	10		T64	26
values[4]	3031	1			T13	14		T56	8		T280	2
values[5]	3548	1			T137	6		T114	4		T58	21
values[6]	3595	1			T21	87		T55	84		T94	8
values[7]	4027	1			T16	20		T57	16		T178	16

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	342	1			T22	10		T209	4		T66	12
auto[0]	values[0]	values[1]	270	1			T68	14		T218	10		T181	10
auto[0]	values[0]	values[2]	245	1			T177	8		T281	6		T215	40
auto[0]	values[0]	values[3]	278	1			T64	26		T66	12		T237	16
auto[0]	values[0]	values[4]	77	1			T65	10		T282	10		T272	12
auto[0]	values[0]	values[5]	184	1			T137	6		T283	30		T284	6
auto[0]	values[0]	values[6]	177	1			T66	8		T218	31		T285	6
auto[0]	values[0]	values[7]	341	1			T265	14		T50	21		T262	13
auto[0]	values[1]	values[0]	184	1			T60	14		T67	9		T69	13
auto[0]	values[1]	values[1]	252	1			T286	4		T287	16		T288	25
auto[0]	values[1]	values[2]	321	1			T179	8		T190	14		T237	20
auto[0]	values[1]	values[3]	252	1			T17	2		T109	16		T213	4
auto[0]	values[1]	values[4]	131	1			T289	12		T172	22		T290	9
auto[0]	values[1]	values[5]	363	1			T66	11		T218	61		T237	6
auto[0]	values[1]	values[6]	374	1			T55	84		T181	29		T171	16
auto[0]	values[1]	values[7]	307	1			T178	16		T67	9		T184	8
auto[0]	values[2]	values[0]	505	1			T58	14		T218	13		T262	12
auto[0]	values[2]	values[1]	302	1			T182	15		T291	6		T215	8
auto[0]	values[2]	values[2]	282	1			T65	15		T38	12		T219	11
auto[0]	values[2]	values[3]	301	1			T218	7		T292	63		T215	8
auto[0]	values[2]	values[4]	227	1			T210	12		T293	6		T256	12
auto[0]	values[2]	values[5]	385	1			T254	16		T69	19		T219	9
auto[0]	values[2]	values[6]	294	1			T294	4		T252	4		T295	57
auto[0]	values[2]	values[7]	476	1			T65	15		T69	8		T218	25
auto[0]	values[3]	values[0]	354	1			T296	8		T66	29		T297	23
auto[0]	values[3]	values[1]	307	1			T66	14		T298	12		T218	10
auto[0]	values[3]	values[2]	241	1			T58	10		T66	17		T299	6
auto[0]	values[3]	values[3]	229	1			T300	6		T68	12		T219	11
auto[0]	values[3]	values[4]	206	1			T66	18		T208	10		T301	12
auto[0]	values[3]	values[5]	314	1			T114	4		T65	13		T69	27
auto[0]	values[3]	values[6]	172	1			T21	87		T225	10		T302	28
auto[0]	values[3]	values[7]	214	1			T16	10		T57	16		T58	14
auto[0]	values[4]	values[0]	255	1			T253	16		T303	10		T215	15
auto[0]	values[4]	values[1]	187	1			T240	14		T68	19		T218	36
auto[0]	values[4]	values[2]	411	1			T216	6		T242	14		T68	11
auto[0]	values[4]	values[3]	281	1			T62	77		T65	9		T38	11
auto[0]	values[4]	values[4]	265	1			T38	10		T181	7		T245	20
auto[0]	values[4]	values[5]	213	1			T58	10		T264	12		T50	13
auto[0]	values[4]	values[6]	171	1			T66	8		T218	26		T228	8
auto[0]	values[4]	values[7]	234	1			T66	13		T219	12		T181	11
auto[0]	values[5]	values[0]	352	1			T262	13		T214	9		T304	6
auto[0]	values[5]	values[1]	294	1			T90	22		T38	69		T267	11
auto[0]	values[5]	values[2]	213	1			T24	8		T67	12		T305	6
auto[0]	values[5]	values[3]	283	1			T207	18		T58	11		T306	12
auto[0]	values[5]	values[4]	111	1			T56	8		T38	9		T267	4
auto[0]	values[5]	values[5]	275	1			T307	10		T308	4		T50	33
auto[0]	values[5]	values[6]	372	1			T217	10		T210	102		T225	13
auto[0]	values[5]	values[7]	264	1			T125	6		T180	12		T68	44
auto[0]	values[6]	values[0]	295	1			T69	13		T309	2		T269	22
auto[0]	values[6]	values[1]	155	1			T110	6		T218	7		T261	23
auto[0]	values[6]	values[2]	236	1			T183	26		T222	10		T270	14
auto[0]	values[6]	values[3]	137	1			T65	11		T69	9		T228	27
auto[0]	values[6]	values[4]	315	1			T69	12		T50	9		T267	71
auto[0]	values[6]	values[5]	266	1			T310	4		T191	14		T66	19
auto[0]	values[6]	values[6]	295	1			T94	8		T311	2		T38	10
auto[0]	values[6]	values[7]	175	1			T58	12		T312	20		T313	18
auto[0]	values[7]	values[0]	236	1			T314	36		T182	11		T233	16
auto[0]	values[7]	values[1]	338	1			T65	17		T67	12		T263	2
auto[0]	values[7]	values[2]	154	1			T65	8		T315	10		T270	11
auto[0]	values[7]	values[3]	179	1			T275	22		T91	10		T67	12
auto[0]	values[7]	values[4]	194	1			T280	2		T67	13		T68	16
auto[0]	values[7]	values[5]	118	1			T235	8		T225	11		T316	10
auto[0]	values[7]	values[6]	210	1			T38	12		T182	13		T239	26
auto[0]	values[7]	values[7]	163	1			T37	14		T218	8		T219	5
auto[1]	values[0]	values[0]	162	1			T66	8		T38	6		T68	4
auto[1]	values[0]	values[1]	146	1			T68	10		T218	10		T181	10
auto[1]	values[0]	values[2]	221	1			T177	12		T215	5		T317	2
auto[1]	values[0]	values[3]	195	1			T53	10		T66	12		T237	8
auto[1]	values[0]	values[4]	205	1			T65	150		T87	38		T318	5
auto[1]	values[0]	values[5]	177	1			T223	8		T172	10		T288	20
auto[1]	values[0]	values[6]	172	1			T66	34		T218	19		T319	11
auto[1]	values[0]	values[7]	231	1			T265	37		T50	4		T262	11
auto[1]	values[1]	values[0]	212	1			T67	11		T69	22		T214	12
auto[1]	values[1]	values[1]	157	1			T287	9		T288	7		T320	20
auto[1]	values[1]	values[2]	119	1			T237	2		T50	18		T262	11
auto[1]	values[1]	values[3]	142	1			T210	16		T225	16		T321	7
auto[1]	values[1]	values[4]	158	1			T13	14		T172	8		T290	11
auto[1]	values[1]	values[5]	170	1			T66	16		T250	12		T218	7
auto[1]	values[1]	values[6]	153	1			T181	11		T171	8		T322	18
auto[1]	values[1]	values[7]	246	1			T67	11		T50	20		T295	12
auto[1]	values[2]	values[0]	154	1			T58	6		T323	12		T218	44
auto[1]	values[2]	values[1]	115	1			T182	5		T215	12		T223	6
auto[1]	values[2]	values[2]	220	1			T63	8		T65	5		T38	8
auto[1]	values[2]	values[3]	186	1			T279	6		T218	13		T215	61
auto[1]	values[2]	values[4]	290	1			T210	9		T247	14		T267	64
auto[1]	values[2]	values[5]	138	1			T69	9		T219	11		T261	11
auto[1]	values[2]	values[6]	252	1			T295	6		T324	30		T287	13
auto[1]	values[2]	values[7]	239	1			T65	5		T69	46		T218	9
auto[1]	values[3]	values[0]	196	1			T66	6		T297	2		T270	11
auto[1]	values[3]	values[1]	253	1			T66	14		T218	10		T210	9
auto[1]	values[3]	values[2]	176	1			T58	12		T66	8		T182	62
auto[1]	values[3]	values[3]	138	1			T68	8		T219	9		T262	10
auto[1]	values[3]	values[4]	148	1			T66	8		T236	6		T174	7
auto[1]	values[3]	values[5]	317	1			T65	7		T69	6		T181	13
auto[1]	values[3]	values[6]	68	1			T225	10		T325	16		T302	12
auto[1]	values[3]	values[7]	148	1			T16	10		T58	8		T68	6
auto[1]	values[4]	values[0]	233	1			T215	5		T223	13		T326	20
auto[1]	values[4]	values[1]	182	1			T231	22		T68	5		T218	6
auto[1]	values[4]	values[2]	149	1			T68	21		T327	16		T218	7
auto[1]	values[4]	values[3]	137	1			T65	11		T38	21		T297	10
auto[1]	values[4]	values[4]	244	1			T38	39		T328	6		T181	13
auto[1]	values[4]	values[5]	192	1			T58	11		T264	8		T50	7
auto[1]	values[4]	values[6]	355	1			T66	12		T218	43		T329	12
auto[1]	values[4]	values[7]	348	1			T66	8		T219	8		T181	9
auto[1]	values[5]	values[0]	184	1			T262	7		T214	11		T261	10
auto[1]	values[5]	values[1]	188	1			T38	2		T330	14		T267	9
auto[1]	values[5]	values[2]	213	1			T67	8		T331	26		T287	11
auto[1]	values[5]	values[3]	126	1			T58	9		T38	5		T267	8
auto[1]	values[5]	values[4]	76	1			T38	19		T267	16		T287	7
auto[1]	values[5]	values[5]	127	1			T50	13		T262	6		T214	13
auto[1]	values[5]	values[6]	178	1			T210	8		T225	20		T174	6
auto[1]	values[5]	values[7]	168	1			T59	16		T332	18		T68	8
auto[1]	values[6]	values[0]	145	1			T69	7		T182	10		T331	11
auto[1]	values[6]	values[1]	148	1			T61	24		T218	13		T261	18
auto[1]	values[6]	values[2]	176	1			T333	20		T270	9		T228	13
auto[1]	values[6]	values[3]	326	1			T65	9		T69	11		T228	53
auto[1]	values[6]	values[4]	212	1			T69	9		T50	11		T267	10
auto[1]	values[6]	values[5]	117	1			T66	7		T38	11		T223	5
auto[1]	values[6]	values[6]	191	1			T38	10		T50	10		T290	7
auto[1]	values[6]	values[7]	101	1			T58	13		T244	12		T334	12
auto[1]	values[7]	values[0]	171	1			T182	43		T171	12		T335	11
auto[1]	values[7]	values[1]	271	1			T65	98		T67	8		T267	14
auto[1]	values[7]	values[2]	268	1			T65	132		T270	10		T261	10
auto[1]	values[7]	values[3]	145	1			T67	8		T69	18		T336	2
auto[1]	values[7]	values[4]	172	1			T67	7		T68	20		T50	14
auto[1]	values[7]	values[5]	192	1			T243	16		T225	9		T316	10
auto[1]	values[7]	values[6]	161	1			T38	8		T182	7		T239	9
auto[1]	values[7]	values[7]	372	1			T37	17		T218	129		T219	15