Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	399	1			T22	2		T58	1		T65	4
auto[ReadAddrCrossIntoMailbox]	293	1			T137	2		T253	4		T65	1
auto[ReadAddrCrossOutOfMailbox]	320	1			T137	2		T125	4		T58	2
auto[ReadAddrCrossAllMailbox]	188	1			T58	1		T253	4		T65	4
auto[ReadAddrOutsideMailbox]	3424	1			T13	4		T16	6		T21	8

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2252

1

T13

2

T16

2

T21

4

auto[1]

2372

1

T13

2

T16

4

T21

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	801	1			T16	1		T178	2		T137	4
read_ops[0x0b]	788	1			T13	2		T22	2		T24	2
read_ops[0x3b]	747	1			T13	2		T16	1		T21	6
read_ops[0x6b]	752	1			T16	1		T178	6		T216	2
read_ops[0xbb]	744	1			T16	1		T53	2		T56	2
read_ops[0xeb]	792	1			T16	2		T21	2		T24	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	30	1			T65	1		T191	1		T38	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	41	1			T191	1		T66	1		T68	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T137	1		T65	1		T38	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	17	1			T137	1		T293	1		T228	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	31	1			T137	1		T65	1		T67	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T137	1		T67	1		T219	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	21	1			T69	1		T181	1		T262	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	9	1			T66	1		T262	1		T154	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	280	1			T16	1		T178	1		T60	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	317	1			T178	1		T60	1		T58	4
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	34	1			T22	1		T66	1		T38	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	32	1			T22	1		T65	1		T67	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T253	2		T66	2		T38	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T253	2		T66	1		T38	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	30	1			T125	2		T253	1		T65	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	36	1			T125	2		T253	1		T66	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T253	1		T66	1		T38	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	12	1			T253	1		T67	1		T210	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	272	1			T13	1		T24	1		T178	4
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	312	1			T13	1		T24	1		T178	4
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	23	1			T65	1		T67	1		T272	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	34	1			T218	2		T272	2		T223	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	16	1			T50	1		T215	1		T223	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	34	1			T66	1		T68	1		T219	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	24	1			T58	2		T237	1		T262	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	34	1			T38	1		T50	2		T239	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T65	1		T262	1		T223	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	13	1			T38	1		T210	1		T262	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	270	1			T13	1		T16	1		T21	3
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	283	1			T13	1		T21	3		T53	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	41	1			T68	1		T299	1		T69	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	26	1			T66	2		T265	1		T38	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	18	1			T219	1		T182	2		T50	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T237	1		T181	1		T50	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T38	1		T68	2		T50	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	30	1			T66	1		T67	1		T218	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T65	2		T69	1		T267	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T66	1		T69	2		T215	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	272	1			T178	3		T216	1		T58	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	280	1			T16	1		T178	3		T216	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	20	1			T38	1		T218	1		T210	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	42	1			T58	1		T66	1		T265	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T66	1		T50	1		T225	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T67	1		T262	1		T215	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	20	1			T239	1		T295	2		T326	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T66	1		T270	1		T215	2
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T223	1		T338	1		T339	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T58	1		T65	1		T267	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	274	1			T53	1		T56	1		T62	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	282	1			T16	1		T53	1		T56	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	44	1			T294	1		T67	2		T340	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	32	1			T65	1		T294	1		T340	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	34	1			T69	1		T50	1		T223	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T38	1		T262	1		T297	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	20	1			T69	1		T218	1		T239	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	18	1			T66	1		T69	1		T219	2
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T253	1		T340	1		T50	2
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T253	1		T340	1		T69	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	291	1			T21	1		T24	1		T60	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	291	1			T16	2		T21	1		T24	1