Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4310	1			T21	87		T94	8		T58	20
values[1]	3152	1			T17	2		T53	10		T179	8
values[2]	3996	1			T216	6		T207	18		T341	2
values[3]	3340	1			T178	16		T62	77		T300	6
values[4]	3313	1			T13	14		T16	20		T64	26
values[5]	3623	1			T24	8		T61	24		T60	14
values[6]	3209	1			T22	10		T57	16		T209	4
values[7]	3783	1			T55	84		T56	8		T58	22

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3515	1			T216	6		T300	6		T180	12
values[1]	3461	1			T57	16		T55	84		T137	6
values[2]	3872	1			T56	8		T179	8		T58	20
values[3]	3966	1			T13	14		T21	87		T53	10
values[4]	3750	1			T24	8		T178	16		T207	18
values[5]	3796	1			T16	20		T58	22		T311	2
values[6]	2981	1			T22	10		T60	14		T58	46
values[7]	3385	1			T17	2		T94	8		T114	4

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27957

1

T13

12

T16

19

T17

2

auto[1]

769

1

T13

2

T16

1

T53

4

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	484	1			T38	98		T292	63		T342	14
auto[0]	values[0]	values[1]	402	1			T58	20		T67	16		T210	43
auto[0]	values[0]	values[2]	628	1			T256	12		T282	10		T270	21
auto[0]	values[0]	values[3]	807	1			T21	87		T343	2		T69	31
auto[0]	values[0]	values[4]	594	1			T66	25		T344	16		T50	19
auto[0]	values[0]	values[5]	389	1			T311	2		T218	18		T50	18
auto[0]	values[0]	values[6]	433	1			T275	22		T296	8		T285	6
auto[0]	values[0]	values[7]	457	1			T94	8		T66	27		T270	44
auto[0]	values[1]	values[0]	398	1			T38	24		T213	4		T181	18
auto[0]	values[1]	values[1]	298	1			T50	20		T214	20		T261	20
auto[0]	values[1]	values[2]	284	1			T179	8		T69	54		T301	12
auto[0]	values[1]	values[3]	291	1			T53	6		T66	25		T242	14
auto[0]	values[1]	values[4]	594	1			T183	26		T328	6		T68	20
auto[0]	values[1]	values[5]	497	1			T240	14		T337	12		T333	20
auto[0]	values[1]	values[6]	310	1			T327	16		T182	20		T302	19
auto[0]	values[1]	values[7]	412	1			T17	2		T59	16		T65	20
auto[0]	values[2]	values[0]	587	1			T216	6		T341	2		T283	30
auto[0]	values[2]	values[1]	342	1			T254	16		T262	48		T267	16
auto[0]	values[2]	values[2]	409	1			T250	6		T264	20		T261	22
auto[0]	values[2]	values[3]	585	1			T277	69		T218	108		T219	19
auto[0]	values[2]	values[4]	668	1			T207	18		T65	160		T345	2
auto[0]	values[2]	values[5]	649	1			T218	41		T227	18		T215	42
auto[0]	values[2]	values[6]	290	1			T332	18		T50	21		T228	19
auto[0]	values[2]	values[7]	366	1			T218	20		T262	20		T267	76
auto[0]	values[3]	values[0]	350	1			T300	6		T38	20		T214	18
auto[0]	values[3]	values[1]	376	1			T331	52		T316	51		T287	23
auto[0]	values[3]	values[2]	458	1			T68	20		T218	33		T255	4
auto[0]	values[3]	values[3]	352	1			T231	22		T91	10		T310	4
auto[0]	values[3]	values[4]	352	1			T178	16		T218	28		T267	20
auto[0]	values[3]	values[5]	498	1			T69	17		T237	23		T210	27
auto[0]	values[3]	values[6]	353	1			T222	10		T67	16		T346	2
auto[0]	values[3]	values[7]	507	1			T62	77		T37	29		T286	4
auto[0]	values[4]	values[0]	663	1			T307	10		T66	31		T262	61
auto[0]	values[4]	values[1]	423	1			T137	6		T125	6		T306	12
auto[0]	values[4]	values[2]	383	1			T65	20		T38	72		T239	20
auto[0]	values[4]	values[3]	302	1			T13	12		T64	26		T65	20
auto[0]	values[4]	values[4]	359	1			T299	6		T245	20		T347	20
auto[0]	values[4]	values[5]	398	1			T16	19		T90	22		T340	6
auto[0]	values[4]	values[6]	409	1			T218	135		T228	76		T348	49
auto[0]	values[4]	values[7]	285	1			T237	24		T315	10		T87	58
auto[0]	values[5]	values[0]	318	1			T244	10		T324	21		T85	18
auto[0]	values[5]	values[1]	316	1			T284	6		T262	35		T228	40
auto[0]	values[5]	values[2]	540	1			T219	20		T309	2		T262	99
auto[0]	values[5]	values[3]	564	1			T61	24		T63	6		T291	6
auto[0]	values[5]	values[4]	443	1			T24	8		T58	20		T66	47
auto[0]	values[5]	values[5]	496	1			T232	16		T349	63		T297	58
auto[0]	values[5]	values[6]	373	1			T60	14		T58	21		T236	6
auto[0]	values[5]	values[7]	458	1			T114	4		T280	2		T68	44
auto[0]	values[6]	values[0]	367	1			T305	6		T230	2		T182	22
auto[0]	values[6]	values[1]	334	1			T57	16		T269	22		T308	4
auto[0]	values[6]	values[2]	533	1			T58	20		T38	27		T50	47
auto[0]	values[6]	values[3]	496	1			T209	4		T314	36		T218	55
auto[0]	values[6]	values[4]	295	1			T350	6		T351	12		T331	20
auto[0]	values[6]	values[5]	387	1			T66	42		T38	20		T68	36
auto[0]	values[6]	values[6]	385	1			T22	10		T58	25		T190	14
auto[0]	values[6]	values[7]	318	1			T298	12		T218	20		T181	19
auto[0]	values[7]	values[0]	238	1			T180	12		T214	19		T215	20
auto[0]	values[7]	values[1]	881	1			T55	84		T65	92		T66	21
auto[0]	values[7]	values[2]	516	1			T56	8		T253	16		T65	19
auto[0]	values[7]	values[3]	481	1			T279	6		T65	20		T68	56
auto[0]	values[7]	values[4]	349	1			T67	19		T110	6		T182	90
auto[0]	values[7]	values[5]	394	1			T58	22		T191	14		T208	10
auto[0]	values[7]	values[6]	343	1			T218	19		T177	19		T261	20
auto[0]	values[7]	values[7]	490	1			T65	156		T66	16		T323	12
auto[1]	values[0]	values[0]	17	1			T38	5		T225	4		T295	3
auto[1]	values[0]	values[1]	13	1			T67	4		T210	1		T287	2
auto[1]	values[0]	values[2]	18	1			T215	2		T74	1		T87	1
auto[1]	values[0]	values[3]	21	1			T50	1		T228	5		T322	1
auto[1]	values[0]	values[4]	10	1			T66	2		T50	1		T352	1
auto[1]	values[0]	values[5]	9	1			T218	2		T50	2		T326	1
auto[1]	values[0]	values[6]	14	1			T181	1		T324	2		T316	2
auto[1]	values[0]	values[7]	14	1			T66	1		T353	7		T212	3
auto[1]	values[1]	values[0]	16	1			T181	2		T326	2		T154	1
auto[1]	values[1]	values[1]	5	1			T172	2		T354	1		T355	1
auto[1]	values[1]	values[2]	3	1			T319	3		-	-		-	-
auto[1]	values[1]	values[3]	13	1			T53	4		T66	1		T181	1
auto[1]	values[1]	values[4]	13	1			T290	1		T74	1		T326	1
auto[1]	values[1]	values[5]	4	1			T172	1		T356	3		-	-
auto[1]	values[1]	values[6]	3	1			T302	1		T357	1		T355	1
auto[1]	values[1]	values[7]	11	1			T69	1		T50	2		T329	2
auto[1]	values[2]	values[0]	13	1			T182	3		T171	2		T358	2
auto[1]	values[2]	values[1]	17	1			T262	5		T267	4		T334	2
auto[1]	values[2]	values[2]	22	1			T250	6		T321	1		T288	1
auto[1]	values[2]	values[3]	8	1			T218	2		T219	1		T295	3
auto[1]	values[2]	values[4]	7	1			T223	1		T313	1		T359	2
auto[1]	values[2]	values[5]	9	1			T174	2		T320	2		T360	1
auto[1]	values[2]	values[6]	18	1			T50	2		T228	1		T331	1
auto[1]	values[2]	values[7]	6	1			T267	1		T223	2		T171	1
auto[1]	values[3]	values[0]	8	1			T214	2		T321	2		T288	1
auto[1]	values[3]	values[1]	5	1			T316	2		T361	1		T362	2
auto[1]	values[3]	values[2]	19	1			T218	1		T363	1		T364	1
auto[1]	values[3]	values[3]	8	1			T218	2		T261	2		T363	1
auto[1]	values[3]	values[4]	13	1			T81	2		T321	1		T313	1
auto[1]	values[3]	values[5]	13	1			T69	3		T237	1		T330	2
auto[1]	values[3]	values[6]	15	1			T67	4		T290	1		T288	4
auto[1]	values[3]	values[7]	13	1			T37	2		T219	3		T215	2
auto[1]	values[4]	values[0]	22	1			T66	4		T262	3		T267	1
auto[1]	values[4]	values[1]	9	1			T365	2		T352	1		T366	2
auto[1]	values[4]	values[2]	7	1			T295	2		T319	2		T313	2
auto[1]	values[4]	values[3]	4	1			T13	2		T219	1		T367	1
auto[1]	values[4]	values[4]	14	1			T262	2		T74	1		T363	2
auto[1]	values[4]	values[5]	12	1			T16	1		T210	1		T290	1
auto[1]	values[4]	values[6]	10	1			T218	2		T228	2		T320	2
auto[1]	values[4]	values[7]	13	1			T237	2		T87	3		T368	1
auto[1]	values[5]	values[0]	11	1			T244	2		T324	1		T369	1
auto[1]	values[5]	values[1]	6	1			T360	3		T367	1		T370	2
auto[1]	values[5]	values[2]	29	1			T262	6		T243	6		T225	3
auto[1]	values[5]	values[3]	15	1			T63	2		T262	1		T214	3
auto[1]	values[5]	values[4]	16	1			T58	2		T67	2		T69	2
auto[1]	values[5]	values[5]	15	1			T225	4		T228	1		T366	3
auto[1]	values[5]	values[6]	7	1			T181	1		T331	1		T371	2
auto[1]	values[5]	values[7]	16	1			T219	1		T287	4		T288	3
auto[1]	values[6]	values[0]	15	1			T182	1		T297	1		T225	3
auto[1]	values[6]	values[1]	13	1			T270	2		T359	1		T226	1
auto[1]	values[6]	values[2]	15	1			T38	1		T171	1		T316	2
auto[1]	values[6]	values[3]	13	1			T218	2		T267	1		T223	1
auto[1]	values[6]	values[4]	10	1			T174	1		T313	4		T362	1
auto[1]	values[6]	values[5]	12	1			T228	3		T331	1		T318	1
auto[1]	values[6]	values[6]	9	1			T363	3		T326	2		T352	2
auto[1]	values[6]	values[7]	7	1			T181	1		T214	2		T174	1
auto[1]	values[7]	values[0]	8	1			T214	1		T223	2		T331	1
auto[1]	values[7]	values[1]	21	1			T65	3		T66	3		T68	3
auto[1]	values[7]	values[2]	8	1			T65	1		T215	3		T372	2
auto[1]	values[7]	values[3]	6	1			T69	1		T373	2		T77	3
auto[1]	values[7]	values[4]	13	1			T67	1		T182	4		T287	1
auto[1]	values[7]	values[5]	14	1			T267	1		T374	1		T375	1
auto[1]	values[7]	values[6]	9	1			T218	1		T177	1		T261	1
auto[1]	values[7]	values[7]	12	1			T65	4		T66	4		T376	1