Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	838	1			T25	17		T35	4		T37	10
all_values[1]	838	1			T25	17		T35	4		T37	10
all_values[2]	838	1			T25	17		T35	4		T37	10
all_values[3]	838	1			T25	17		T35	4		T37	10
all_values[4]	838	1			T25	17		T35	4		T37	10
all_values[5]	838	1			T25	17		T35	4		T37	10
all_values[6]	838	1			T25	17		T35	4		T37	10
all_values[7]	838	1			T25	17		T35	4		T37	10

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3505

1

T25

71

T35

24

T37

42

auto[1]

3199

1

T25

65

T35

8

T37

38

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2664

1

T25

44

T35

17

T37

24

auto[1]

4040

1

T25

92

T35

15

T37

56

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3824

1

T25

67

T35

21

T37

41

auto[1]

2880

1

T25

69

T35

11

T37

39

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	161	1			T25	3		T35	2		T37	1
all_values[0]	auto[0]	auto[0]	auto[1]	78	1			T25	1		T35	1		T37	2
all_values[0]	auto[0]	auto[1]	auto[0]	142	1			T38	4		T177	2		T50	2
all_values[0]	auto[0]	auto[1]	auto[1]	91	1			T25	2		T37	2		T38	2
all_values[0]	auto[1]	auto[0]	auto[1]	194	1			T25	9		T35	1		T37	2
all_values[0]	auto[1]	auto[1]	auto[1]	172	1			T25	2		T37	3		T38	2
all_values[1]	auto[0]	auto[0]	auto[0]	157	1			T25	1		T35	2		T37	2
all_values[1]	auto[0]	auto[0]	auto[1]	79	1			T25	3		T35	1		T38	1
all_values[1]	auto[0]	auto[1]	auto[0]	139	1			T25	1		T37	1		T177	2
all_values[1]	auto[0]	auto[1]	auto[1]	106	1			T25	2		T37	3		T38	1
all_values[1]	auto[1]	auto[0]	auto[1]	200	1			T25	6		T35	1		T38	3
all_values[1]	auto[1]	auto[1]	auto[1]	157	1			T25	4		T37	4		T38	1
all_values[2]	auto[0]	auto[0]	auto[0]	167	1			T25	1		T35	1		T37	1
all_values[2]	auto[0]	auto[0]	auto[1]	100	1			T25	3		T37	2		T38	1
all_values[2]	auto[0]	auto[1]	auto[0]	145	1			T25	5		T35	1		T37	1
all_values[2]	auto[0]	auto[1]	auto[1]	71	1			T37	1		T38	2		T177	2
all_values[2]	auto[1]	auto[0]	auto[1]	187	1			T25	3		T35	1		T37	3
all_values[2]	auto[1]	auto[1]	auto[1]	168	1			T25	5		T35	1		T37	2
all_values[3]	auto[0]	auto[0]	auto[0]	178	1			T25	2		T35	2		T37	2
all_values[3]	auto[0]	auto[0]	auto[1]	71	1			T25	1		T38	2		T177	1
all_values[3]	auto[0]	auto[1]	auto[0]	157	1			T25	4		T37	4		T38	2
all_values[3]	auto[0]	auto[1]	auto[1]	81	1			T25	2		T38	1		T177	3
all_values[3]	auto[1]	auto[0]	auto[1]	176	1			T25	5		T35	1		T37	1
all_values[3]	auto[1]	auto[1]	auto[1]	175	1			T25	3		T35	1		T37	3
all_values[4]	auto[0]	auto[0]	auto[0]	172	1			T25	2		T35	1		T37	3
all_values[4]	auto[0]	auto[0]	auto[1]	66	1			T38	2		T177	1		T170	2
all_values[4]	auto[0]	auto[1]	auto[0]	156	1			T25	5		T35	2		T38	1
all_values[4]	auto[0]	auto[1]	auto[1]	94	1			T25	2		T37	2		T38	2
all_values[4]	auto[1]	auto[0]	auto[1]	180	1			T25	1		T35	1		T37	2
all_values[4]	auto[1]	auto[1]	auto[1]	170	1			T25	7		T37	3		T38	4
all_values[5]	auto[0]	auto[0]	auto[0]	255	1			T25	4		T35	2		T37	2
all_values[5]	auto[0]	auto[1]	auto[0]	214	1			T25	4		T37	1		T38	2
all_values[5]	auto[1]	auto[0]	auto[1]	220	1			T25	5		T35	1		T37	4
all_values[5]	auto[1]	auto[1]	auto[1]	149	1			T25	4		T35	1		T37	3
all_values[6]	auto[0]	auto[0]	auto[0]	179	1			T25	4		T35	4		T37	3
all_values[6]	auto[0]	auto[0]	auto[1]	88	1			T25	4		T37	2		T177	1
all_values[6]	auto[0]	auto[1]	auto[0]	145	1			T25	2		T38	4		T177	2
all_values[6]	auto[0]	auto[1]	auto[1]	77	1			T25	1		T37	1		T38	1
all_values[6]	auto[1]	auto[0]	auto[1]	159	1			T25	4		T37	3		T38	1
all_values[6]	auto[1]	auto[1]	auto[1]	190	1			T25	2		T37	1		T38	5
all_values[7]	auto[0]	auto[0]	auto[0]	163	1			T25	3		T37	3		T38	3
all_values[7]	auto[0]	auto[0]	auto[1]	79	1			T35	1		T37	2		T38	2
all_values[7]	auto[0]	auto[1]	auto[0]	134	1			T25	3		T38	1		T177	1
all_values[7]	auto[0]	auto[1]	auto[1]	79	1			T25	2		T35	1		T38	1
all_values[7]	auto[1]	auto[0]	auto[1]	196	1			T25	6		T35	1		T37	2
all_values[7]	auto[1]	auto[1]	auto[1]	187	1			T25	3		T35	1		T37	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal