Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1779

1

T9

1

T14

6

T27

5

auto[1]

1797

1

T2

2

T9

2

T14

12

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1980

1

T31

10

T46

11

T35

4

auto[1]

1596

1

T2

2

T9

3

T14

18

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2791

1

T2

2

T9

3

T14

18

auto[1]

785

1

T31

3

T46

4

T35

3

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	721	1			T2	1		T14	3		T27	5
valid[1]	736	1			T14	8		T27	1		T29	2
valid[2]	715	1			T2	1		T9	1		T14	1
valid[3]	690	1			T9	1		T14	2		T27	2
valid[4]	714	1			T9	1		T14	4		T27	5

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	105	1			T89	1		T385	2		T187	1
auto[0]	auto[0]	valid[0]	auto[1]	159	1			T14	1		T27	1		T29	7
auto[0]	auto[0]	valid[1]	auto[0]	103	1			T31	1		T71	1		T72	1
auto[0]	auto[0]	valid[1]	auto[1]	161	1			T14	3		T30	2		T32	3
auto[0]	auto[0]	valid[2]	auto[0]	123	1			T31	1		T46	2		T71	1
auto[0]	auto[0]	valid[2]	auto[1]	158	1			T14	1		T29	7		T30	1
auto[0]	auto[0]	valid[3]	auto[0]	128	1			T31	2		T46	2		T35	1
auto[0]	auto[0]	valid[3]	auto[1]	147	1			T27	1		T29	2		T30	2
auto[0]	auto[0]	valid[4]	auto[0]	120	1			T71	2		T58	1		T89	1
auto[0]	auto[0]	valid[4]	auto[1]	168	1			T9	1		T14	1		T27	3
auto[0]	auto[1]	valid[0]	auto[0]	127	1			T46	1		T58	1		T89	1
auto[0]	auto[1]	valid[0]	auto[1]	161	1			T2	1		T14	2		T27	4
auto[0]	auto[1]	valid[1]	auto[0]	142	1			T31	1		T46	1		T71	1
auto[0]	auto[1]	valid[1]	auto[1]	162	1			T14	5		T27	1		T29	2
auto[0]	auto[1]	valid[2]	auto[0]	118	1			T31	1		T46	1		T389	3
auto[0]	auto[1]	valid[2]	auto[1]	167	1			T2	1		T9	1		T27	1
auto[0]	auto[1]	valid[3]	auto[0]	120	1			T31	1		T73	1		T89	3
auto[0]	auto[1]	valid[3]	auto[1]	152	1			T9	1		T14	2		T27	1
auto[0]	auto[1]	valid[4]	auto[0]	109	1			T389	1		T188	1		T393	1
auto[0]	auto[1]	valid[4]	auto[1]	161	1			T14	3		T27	2		T29	3
auto[1]	auto[0]	valid[0]	auto[0]	83	1			T46	1		T35	1		T72	2
auto[1]	auto[0]	valid[1]	auto[0]	79	1			T71	2		T72	1		T73	1
auto[1]	auto[0]	valid[2]	auto[0]	79	1			T46	1		T35	1		T71	1
auto[1]	auto[0]	valid[3]	auto[0]	74	1			T31	2		T46	1		T72	2
auto[1]	auto[0]	valid[4]	auto[0]	92	1			T71	1		T72	1		T388	1
auto[1]	auto[1]	valid[0]	auto[0]	86	1			T71	1		T73	1		T58	1
auto[1]	auto[1]	valid[1]	auto[0]	89	1			T46	1		T71	1		T73	1
auto[1]	auto[1]	valid[2]	auto[0]	70	1			T72	1		T58	1		T89	1
auto[1]	auto[1]	valid[3]	auto[0]	69	1			T31	1		T35	1		T73	1
auto[1]	auto[1]	valid[4]	auto[0]	64	1			T89	1		T188	1		T186	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal