Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

51108

1

T4

1

T11

7

T28

13

auto[1]

16681

1

T2

2

T9

3

T14

311

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49133

1

T2

2

T9

3

T11

4

auto[1]

18656

1

T4

1

T11

3

T28

6

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	35010	1			T2	2		T4	1		T9	3
others[1]	5779	1			T11	2		T14	33		T29	30
others[2]	5557	1			T14	25		T28	1		T29	37
others[3]	6483	1			T11	2		T14	23		T28	3
interest[1]	3655	1			T14	17		T29	31		T30	11
interest[4]	22993	1			T2	2		T4	1		T9	3
interest[64]	11305	1			T11	2		T14	54		T29	69

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	16606	1			T28	6		T31	52		T45	5
auto[0]	auto[0]	others[1]	2789	1			T11	2		T31	13		T46	14
auto[0]	auto[0]	others[2]	2649	1			T31	13		T45	1		T46	4
auto[0]	auto[0]	others[3]	3124	1			T11	2		T28	1		T31	13
auto[0]	auto[0]	interest[1]	1747	1			T31	10		T46	5		T35	2
auto[0]	auto[0]	interest[4]	10913	1			T28	3		T31	41		T45	4
auto[0]	auto[0]	interest[64]	5537	1			T31	29		T45	1		T46	25
auto[0]	auto[1]	others[0]	8667	1			T2	2		T9	3		T14	159
auto[0]	auto[1]	others[1]	1472	1			T14	33		T29	30		T30	30
auto[0]	auto[1]	others[2]	1358	1			T14	25		T29	37		T30	21
auto[0]	auto[1]	others[3]	1580	1			T14	23		T29	35		T30	27
auto[0]	auto[1]	interest[1]	865	1			T14	17		T29	31		T30	11
auto[0]	auto[1]	interest[4]	5748	1			T2	2		T9	3		T14	110
auto[0]	auto[1]	interest[64]	2739	1			T14	54		T29	69		T30	42
auto[1]	auto[0]	others[0]	9737	1			T4	1		T11	1		T28	3
auto[1]	auto[0]	others[1]	1518	1			T31	2		T45	2		T46	7
auto[1]	auto[0]	others[2]	1550	1			T28	1		T31	3		T46	10
auto[1]	auto[0]	others[3]	1779	1			T28	2		T31	2		T46	5
auto[1]	auto[0]	interest[1]	1043	1			T31	4		T46	9		T35	1
auto[1]	auto[0]	interest[4]	6332	1			T4	1		T11	1		T28	2
auto[1]	auto[0]	interest[64]	3029	1			T11	2		T31	11		T45	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal