Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2835363	1			T1	1		T2	1		T3	1
all_values[1]	2835363	1			T1	1		T2	1		T3	1
all_values[2]	2835363	1			T1	1		T2	1		T3	1
all_values[3]	2835363	1			T1	1		T2	1		T3	1
all_values[4]	2835363	1			T1	1		T2	1		T3	1
all_values[5]	2835363	1			T1	1		T2	1		T3	1
all_values[6]	2835363	1			T1	1		T2	1		T3	1
all_values[7]	2835363	1			T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22337485

1

T1

8

T2

8

T3

8

auto[1]

345419

1

T33

88

T34

1327

T36

143

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22657830

1

T1

8

T2

8

T3

8

auto[1]

25074

1

T33

59

T34

61

T51

207

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2822539	1			T1	1		T2	1		T3	1
all_values[0]	auto[0]	auto[1]	11923	1			T33	4		T34	4		T51	74
all_values[0]	auto[1]	auto[0]	719	1			T33	3		T34	426		T36	14
all_values[0]	auto[1]	auto[1]	182	1			T33	3		T34	3		T36	7
all_values[1]	auto[0]	auto[0]	2746883	1			T1	1		T2	1		T3	1
all_values[1]	auto[0]	auto[1]	7469	1			T33	6		T34	8		T51	70
all_values[1]	auto[1]	auto[0]	80474	1			T33	2		T34	4		T36	10
all_values[1]	auto[1]	auto[1]	537	1			T33	7		T34	2		T36	3
all_values[2]	auto[0]	auto[0]	2794423	1			T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	2698	1			T33	1		T34	2		T51	63
all_values[2]	auto[1]	auto[0]	37930	1			T33	9		T34	425		T36	6
all_values[2]	auto[1]	auto[1]	312	1			T33	4		T34	5		T36	10
all_values[3]	auto[0]	auto[0]	2815632	1			T1	1		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	213	1			T33	2		T34	1		T36	5
all_values[3]	auto[1]	auto[0]	19331	1			T33	4		T34	4		T36	16
all_values[3]	auto[1]	auto[1]	187	1			T33	4		T34	8		T36	3
all_values[4]	auto[0]	auto[0]	2791183	1			T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	203	1			T33	2		T34	7		T36	6
all_values[4]	auto[1]	auto[0]	43791	1			T33	10		T34	2		T36	7
all_values[4]	auto[1]	auto[1]	186	1			T33	2		T34	2		T36	4
all_values[5]	auto[0]	auto[0]	2779226	1			T1	1		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	186	1			T33	4		T34	3		T36	9
all_values[5]	auto[1]	auto[0]	55770	1			T33	8		T34	6		T36	14
all_values[5]	auto[1]	auto[1]	181	1			T33	5		T34	1		T36	7
all_values[6]	auto[0]	auto[0]	2807332	1			T1	1		T2	1		T3	1
all_values[6]	auto[0]	auto[1]	194	1			T33	2		T34	4		T36	5
all_values[6]	auto[1]	auto[0]	27634	1			T33	7		T34	2		T36	15
all_values[6]	auto[1]	auto[1]	203	1			T33	4		T34	4		T36	8
all_values[7]	auto[0]	auto[0]	2757193	1			T1	1		T2	1		T3	1
all_values[7]	auto[0]	auto[1]	188	1			T33	2		T34	3		T36	5
all_values[7]	auto[1]	auto[0]	77770	1			T33	9		T34	429		T36	13
all_values[7]	auto[1]	auto[1]	212	1			T33	7		T34	4		T36	6