Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.08 98.45 94.10 98.62 89.36 97.29 95.56 99.21


Total tests in report: 1151
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
49.62 49.62 76.18 76.18 50.52 50.52 55.22 55.22 22.22 22.22 59.98 59.98 73.19 73.19 10.00 10.00 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_all.4121356149
74.47 24.85 96.56 20.38 87.24 36.72 78.64 23.43 62.22 40.00 94.45 34.46 83.89 10.69 18.27 8.27 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/1.spi_device_upload.3705353501
80.50 6.04 97.33 0.77 89.23 1.99 80.91 2.26 80.00 17.78 95.55 1.10 84.03 0.14 36.49 18.22 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/3.spi_device_stress_all.1887592235
83.69 3.19 97.76 0.43 90.85 1.63 90.75 9.84 86.67 6.67 96.31 0.76 85.00 0.97 38.51 2.03 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/1.spi_device_pass_cmd_filtering.3344535477
85.74 2.05 98.03 0.27 91.87 1.02 90.75 0.00 88.89 2.22 96.68 0.37 85.14 0.14 48.81 10.30 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.96006768
87.35 1.61 98.03 0.00 91.87 0.00 90.75 0.00 88.89 0.00 96.68 0.00 85.14 0.00 60.10 11.29 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/0.spi_device_stress_all.3060811240
88.88 1.53 98.03 0.00 92.00 0.12 91.14 0.39 88.89 0.00 96.71 0.03 93.61 8.47 61.78 1.68 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1824279665
90.23 1.35 98.11 0.08 92.03 0.04 91.14 0.00 91.11 2.22 96.83 0.12 93.61 0.00 68.76 6.98 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.1146998247
91.12 0.89 98.12 0.01 92.08 0.05 91.14 0.00 93.33 2.22 96.85 0.02 93.61 0.00 72.72 3.96 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_all.2639378477
91.88 0.76 98.12 0.00 92.08 0.00 91.14 0.00 93.33 0.00 96.85 0.00 93.61 0.00 78.02 5.30 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_and_tpm.105700764
92.56 0.68 98.13 0.01 92.08 0.00 95.87 4.72 93.33 0.00 96.85 0.00 93.61 0.00 78.02 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/0.spi_device_ram_cfg.4225793900
92.98 0.42 98.25 0.12 92.69 0.61 95.87 0.00 93.33 0.00 97.02 0.17 94.17 0.56 79.50 1.49 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/0.spi_device_read_buffer_direct.1188656693
93.38 0.40 98.25 0.00 92.71 0.01 95.87 0.00 93.33 0.00 97.02 0.00 94.17 0.00 82.33 2.82 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_all.3103834046
93.75 0.37 98.26 0.01 92.74 0.04 98.03 2.17 93.33 0.00 97.04 0.02 94.31 0.14 82.57 0.25 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/0.spi_device_sec_cm.2574822025
94.06 0.30 98.26 0.00 92.74 0.00 98.03 0.00 93.33 0.00 97.04 0.00 94.31 0.00 84.70 2.13 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_and_tpm.1737737479
94.34 0.28 98.29 0.03 92.78 0.04 98.03 0.00 93.33 0.00 97.10 0.07 94.31 0.00 86.53 1.83 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_and_tpm_min_idle.4246103487
94.61 0.27 98.29 0.00 92.78 0.00 98.03 0.00 93.33 0.00 97.10 0.00 94.44 0.14 88.32 1.78 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_and_tpm_min_idle.2422154273
94.77 0.16 98.29 0.00 92.83 0.05 98.03 0.00 93.33 0.00 97.14 0.03 94.44 0.00 89.36 1.04 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_mode_ignore_cmds.3597707813
94.93 0.15 98.29 0.00 92.87 0.04 98.03 0.00 93.33 0.00 97.14 0.00 94.44 0.00 90.40 1.04 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_read_hw_reg.3976247008
95.08 0.15 98.30 0.01 92.90 0.04 98.03 0.00 93.33 0.00 97.15 0.02 94.44 0.00 91.39 0.99 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_intg_err.3025791277
95.21 0.13 98.30 0.00 92.90 0.00 98.03 0.00 93.33 0.00 97.15 0.00 94.44 0.00 92.33 0.94 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_mode_ignore_cmds.231772104
95.34 0.13 98.30 0.00 93.66 0.76 98.03 0.00 93.33 0.00 97.15 0.00 94.44 0.00 92.48 0.15 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_errors.59618479
95.46 0.12 98.30 0.00 93.66 0.00 98.03 0.00 93.33 0.00 97.15 0.00 95.28 0.83 92.48 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_aliasing.242306827
95.58 0.11 98.30 0.00 93.67 0.01 98.03 0.00 93.33 0.00 97.15 0.00 95.28 0.00 93.27 0.79 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_mode_ignore_cmds.3982214454
95.69 0.11 98.30 0.00 93.69 0.01 98.03 0.00 93.33 0.00 97.15 0.00 95.42 0.14 93.91 0.64 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_and_tpm_min_idle.2561873980
95.80 0.11 98.35 0.06 93.77 0.09 98.43 0.39 93.33 0.00 97.24 0.08 95.42 0.00 94.06 0.15 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/0.spi_device_mem_parity.790839642
95.89 0.09 98.35 0.00 93.80 0.02 98.43 0.00 93.33 0.00 97.24 0.00 95.42 0.00 94.65 0.59 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/0.spi_device_cfg_cmd.3343307130
95.96 0.08 98.35 0.00 93.80 0.00 98.43 0.00 93.33 0.00 97.24 0.00 95.56 0.14 95.05 0.40 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/26.spi_device_stress_all.2450142174
96.04 0.07 98.35 0.00 93.80 0.00 98.43 0.00 93.33 0.00 97.24 0.00 95.56 0.00 95.54 0.50 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_all.1534439509
96.10 0.06 98.35 0.00 93.80 0.00 98.43 0.00 93.33 0.00 97.24 0.00 95.56 0.00 95.99 0.45 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/10.spi_device_stress_all.3201248534
96.16 0.06 98.35 0.00 93.80 0.00 98.43 0.00 93.33 0.00 97.24 0.00 95.56 0.00 96.39 0.40 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/32.spi_device_stress_all.30074983
96.20 0.04 98.35 0.00 93.80 0.00 98.43 0.00 93.33 0.00 97.24 0.00 95.56 0.00 96.68 0.30 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode.3146808311
96.24 0.04 98.36 0.01 93.80 0.00 98.43 0.00 93.33 0.00 97.26 0.02 95.56 0.00 96.93 0.25 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_all.3505553966
96.27 0.04 98.39 0.03 93.84 0.04 98.62 0.20 93.33 0.00 97.26 0.00 95.56 0.00 96.93 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/0.spi_device_alert_test.3309193861
96.31 0.04 98.39 0.00 94.00 0.16 98.62 0.00 93.33 0.00 97.26 0.00 95.56 0.00 97.03 0.10 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.1101640065
96.35 0.04 98.39 0.00 94.00 0.00 98.62 0.00 93.33 0.00 97.26 0.00 95.56 0.00 97.28 0.25 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/13.spi_device_stress_all.3297136462
96.38 0.04 98.39 0.00 94.00 0.00 98.62 0.00 93.33 0.00 97.26 0.00 95.56 0.00 97.52 0.25 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_and_tpm_min_idle.688673921
96.41 0.03 98.39 0.00 94.00 0.00 98.62 0.00 93.33 0.00 97.26 0.00 95.56 0.00 97.72 0.20 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_mode_ignore_cmds.3991029057
96.44 0.03 98.39 0.00 94.00 0.00 98.62 0.00 93.33 0.00 97.26 0.00 95.56 0.00 97.92 0.20 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_and_tpm.2349805091
96.46 0.02 98.44 0.05 94.04 0.04 98.62 0.00 93.33 0.00 97.27 0.02 95.56 0.00 97.97 0.05 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/2.spi_device_stress_all.3184170033
96.48 0.02 98.44 0.00 94.04 0.00 98.62 0.00 93.33 0.00 97.27 0.00 95.56 0.00 98.12 0.15 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_and_tpm_min_idle.3707749543
96.50 0.02 98.44 0.00 94.04 0.00 98.62 0.00 93.33 0.00 97.27 0.00 95.56 0.00 98.27 0.15 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/45.spi_device_stress_all.1189885491
96.52 0.01 98.44 0.00 94.04 0.00 98.62 0.00 93.33 0.00 97.27 0.00 95.56 0.00 98.37 0.10 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.2357564994
96.53 0.01 98.44 0.00 94.04 0.00 98.62 0.00 93.33 0.00 97.27 0.00 95.56 0.00 98.47 0.10 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_mode.665226369
96.55 0.01 98.44 0.00 94.04 0.00 98.62 0.00 93.33 0.00 97.27 0.00 95.56 0.00 98.56 0.10 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_and_tpm.2198445334
96.56 0.01 98.44 0.00 94.04 0.00 98.62 0.00 93.33 0.00 97.27 0.00 95.56 0.00 98.66 0.10 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_mode.2819128618
96.57 0.01 98.44 0.00 94.04 0.00 98.62 0.00 93.33 0.00 97.27 0.00 95.56 0.00 98.76 0.10 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_and_tpm_min_idle.3843414745
96.59 0.01 98.44 0.00 94.04 0.00 98.62 0.00 93.33 0.00 97.27 0.00 95.56 0.00 98.86 0.10 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/35.spi_device_stress_all.1156136193
96.60 0.01 98.44 0.00 94.05 0.01 98.62 0.00 93.33 0.00 97.27 0.00 95.56 0.00 98.91 0.05 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.4102869920
96.60 0.01 98.45 0.01 94.07 0.02 98.62 0.00 93.33 0.00 97.29 0.02 95.56 0.00 98.91 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/3.spi_device_pass_cmd_filtering.1466125813
96.61 0.01 98.45 0.00 94.07 0.00 98.62 0.00 93.33 0.00 97.29 0.00 95.56 0.00 98.96 0.05 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_intg_err.1731392581
96.62 0.01 98.45 0.00 94.07 0.00 98.62 0.00 93.33 0.00 97.29 0.00 95.56 0.00 99.01 0.05 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/13.spi_device_upload.3670328934
96.63 0.01 98.45 0.00 94.07 0.00 98.62 0.00 93.33 0.00 97.29 0.00 95.56 0.00 99.06 0.05 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_and_tpm.758579976
96.63 0.01 98.45 0.00 94.07 0.00 98.62 0.00 93.33 0.00 97.29 0.00 95.56 0.00 99.11 0.05 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/18.spi_device_pass_addr_payload_swap.3264233734
96.64 0.01 98.45 0.00 94.07 0.00 98.62 0.00 93.33 0.00 97.29 0.00 95.56 0.00 99.16 0.05 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_and_tpm_min_idle.3314657156
96.65 0.01 98.45 0.00 94.07 0.00 98.62 0.00 93.33 0.00 97.29 0.00 95.56 0.00 99.21 0.05 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/41.spi_device_stress_all.3236214673
96.65 0.01 98.45 0.00 94.10 0.02 98.62 0.00 93.33 0.00 97.29 0.00 95.56 0.00 99.21 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.967490054

Tests that do not contribute to grading

Name   
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.715035471
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3861506606
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.983687087
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.1035863104
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.2611737575
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.1803843241
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.1047233641
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3193503418
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.820043697
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.55421747
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.2280924913
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3357436323
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.875776019
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3736570565
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.57967234
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.1981455436
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.4041014503
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.935606161
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2198579310
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1601744235
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.2093710555
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.3287800680
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.55283629
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.3653485351
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2491141484
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_rw.3556977898
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_intr_test.1478277945
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.657802356
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_errors.3132906657
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_intg_err.2875780697
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.759254368
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/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/6.spi_device_stress_all.1477958236
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_all.3009663223
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_read_hw_reg.1768078114
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_rw.2106855329
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.2088056664
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/6.spi_device_upload.3096064384
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/7.spi_device_alert_test.1255832400
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/7.spi_device_cfg_cmd.1643078666
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/7.spi_device_csb_read.3098923059
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm.1144941381
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.664878077
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode_ignore_cmds.3408312107
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/7.spi_device_intercept.928472164
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mailbox.1491278335
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mem_parity.3975320721
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.2253041388
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.2722012103
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.1560280360
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/7.spi_device_stress_all.2137589078
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_all.227679600
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.1856959559
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_rw.3447958427
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.2829872419
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/7.spi_device_upload.2148763681
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/8.spi_device_alert_test.442097772
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/8.spi_device_cfg_cmd.563457597
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/8.spi_device_csb_read.3539833184
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_all.875102813
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm.511490497
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.512763937
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode.2493186213
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.1476036045
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/8.spi_device_intercept.3158335604
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mailbox.1625373257
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mem_parity.1571684245
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.1196660610
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.3958699247
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.1891107726
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/8.spi_device_stress_all.3591576223
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_all.1217816231
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.376503916
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_rw.4243707288
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_sts_read.2227161456
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/8.spi_device_upload.2028152309
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/9.spi_device_alert_test.4009542470
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/9.spi_device_cfg_cmd.3062152670
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/9.spi_device_csb_read.1394135993
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode.186767090
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.3750581052
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/9.spi_device_intercept.2282961502
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mailbox.1042775386
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mem_parity.2852609342
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.118569929
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.949690714
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.505070112
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/9.spi_device_stress_all.187014894
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_all.2511257056
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.2201054481
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_rw.2682567745
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.2188126886
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/9.spi_device_upload.1617337093



Total test records in report: 1151
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_read_hw_reg.913643281 Sep 18 09:02:38 PM UTC 24 Sep 18 09:02:40 PM UTC 24 14070613 ps
T2 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/0.spi_device_csb_read.321558706 Sep 18 09:02:38 PM UTC 24 Sep 18 09:02:40 PM UTC 24 36368923 ps
T3 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/0.spi_device_ram_cfg.4225793900 Sep 18 09:02:38 PM UTC 24 Sep 18 09:02:41 PM UTC 24 16340148 ps
T4 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/0.spi_device_mem_parity.790839642 Sep 18 09:02:38 PM UTC 24 Sep 18 09:02:41 PM UTC 24 47684587 ps
T5 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_sts_read.2191860005 Sep 18 09:02:38 PM UTC 24 Sep 18 09:02:41 PM UTC 24 67655314 ps
T6 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_all.4121356149 Sep 18 09:02:38 PM UTC 24 Sep 18 09:02:43 PM UTC 24 587201055 ps
T7 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_rw.4222040131 Sep 18 09:02:39 PM UTC 24 Sep 18 09:02:43 PM UTC 24 46891351 ps
T8 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/1.spi_device_csb_read.3726452269 Sep 18 09:02:42 PM UTC 24 Sep 18 09:02:44 PM UTC 24 111252870 ps
T9 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/0.spi_device_alert_test.3309193861 Sep 18 09:02:42 PM UTC 24 Sep 18 09:02:44 PM UTC 24 37988776 ps
T10 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_sts_read.3762932933 Sep 18 09:02:42 PM UTC 24 Sep 18 09:02:45 PM UTC 24 522768565 ps
T26 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/1.spi_device_mem_parity.3790372616 Sep 18 09:02:42 PM UTC 24 Sep 18 09:02:45 PM UTC 24 46582264 ps
T11 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_rw.1191157515 Sep 18 09:02:42 PM UTC 24 Sep 18 09:02:45 PM UTC 24 14436572 ps
T12 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/0.spi_device_sec_cm.2574822025 Sep 18 09:02:42 PM UTC 24 Sep 18 09:02:45 PM UTC 24 317197747 ps
T13 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_mode.436106520 Sep 18 09:02:40 PM UTC 24 Sep 18 09:02:46 PM UTC 24 142276636 ps
T14 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/0.spi_device_read_buffer_direct.1188656693 Sep 18 09:02:40 PM UTC 24 Sep 18 09:02:46 PM UTC 24 514858942 ps
T15 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/0.spi_device_pass_cmd_filtering.1684754520 Sep 18 09:02:39 PM UTC 24 Sep 18 09:02:47 PM UTC 24 397810289 ps
T16 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/0.spi_device_pass_addr_payload_swap.445713973 Sep 18 09:02:39 PM UTC 24 Sep 18 09:02:49 PM UTC 24 5143069959 ps
T17 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/1.spi_device_pass_cmd_filtering.3344535477 Sep 18 09:02:42 PM UTC 24 Sep 18 09:02:50 PM UTC 24 312453946 ps
T18 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/1.spi_device_sec_cm.3201831133 Sep 18 09:02:47 PM UTC 24 Sep 18 09:02:50 PM UTC 24 130320655 ps
T39 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/1.spi_device_alert_test.1736400029 Sep 18 09:02:48 PM UTC 24 Sep 18 09:02:50 PM UTC 24 14919340 ps
T19 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/1.spi_device_read_buffer_direct.2250901751 Sep 18 09:02:47 PM UTC 24 Sep 18 09:02:51 PM UTC 24 93940530 ps
T20 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/2.spi_device_csb_read.370819790 Sep 18 09:02:49 PM UTC 24 Sep 18 09:02:52 PM UTC 24 18404941 ps
T40 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_all.3877333805 Sep 18 09:02:51 PM UTC 24 Sep 18 09:02:53 PM UTC 24 28580469 ps
T44 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/2.spi_device_mem_parity.439629753 Sep 18 09:02:50 PM UTC 24 Sep 18 09:02:53 PM UTC 24 42473387 ps
T27 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_sts_read.1272597949 Sep 18 09:02:52 PM UTC 24 Sep 18 09:02:54 PM UTC 24 76632444 ps
T21 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/1.spi_device_intercept.867170280 Sep 18 09:02:44 PM UTC 24 Sep 18 09:02:54 PM UTC 24 6334958930 ps
T22 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/1.spi_device_cfg_cmd.1631737028 Sep 18 09:02:46 PM UTC 24 Sep 18 09:02:55 PM UTC 24 314784801 ps
T23 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/1.spi_device_pass_addr_payload_swap.3194447741 Sep 18 09:02:43 PM UTC 24 Sep 18 09:02:57 PM UTC 24 7202831367 ps
T28 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_rw.1024734852 Sep 18 09:02:53 PM UTC 24 Sep 18 09:02:57 PM UTC 24 689567540 ps
T24 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/1.spi_device_upload.3705353501 Sep 18 09:02:46 PM UTC 24 Sep 18 09:02:58 PM UTC 24 8427601585 ps
T29 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_read_hw_reg.3976247008 Sep 18 09:02:42 PM UTC 24 Sep 18 09:02:58 PM UTC 24 11500524673 ps
T30 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_read_hw_reg.1995256134 Sep 18 09:02:51 PM UTC 24 Sep 18 09:02:59 PM UTC 24 1109220430 ps
T57 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/2.spi_device_intercept.283161698 Sep 18 09:02:54 PM UTC 24 Sep 18 09:02:59 PM UTC 24 215988590 ps
T83 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/1.spi_device_mailbox.4080109351 Sep 18 09:02:46 PM UTC 24 Sep 18 09:03:00 PM UTC 24 907859415 ps
T56 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/2.spi_device_upload.4152304616 Sep 18 09:02:55 PM UTC 24 Sep 18 09:03:01 PM UTC 24 148776284 ps
T62 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/0.spi_device_upload.2374928800 Sep 18 09:02:39 PM UTC 24 Sep 18 09:03:03 PM UTC 24 19837841652 ps
T25 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/2.spi_device_sec_cm.2931219219 Sep 18 09:03:01 PM UTC 24 Sep 18 09:03:04 PM UTC 24 96459967 ps
T50 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_mode.462111691 Sep 18 09:02:56 PM UTC 24 Sep 18 09:03:04 PM UTC 24 265895248 ps
T107 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/2.spi_device_alert_test.976769674 Sep 18 09:03:02 PM UTC 24 Sep 18 09:03:04 PM UTC 24 26509369 ps
T64 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/2.spi_device_pass_addr_payload_swap.377713743 Sep 18 09:02:54 PM UTC 24 Sep 18 09:03:04 PM UTC 24 1175420816 ps
T101 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/2.spi_device_cfg_cmd.3895907706 Sep 18 09:02:55 PM UTC 24 Sep 18 09:03:06 PM UTC 24 2060855766 ps
T408 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/3.spi_device_csb_read.491717440 Sep 18 09:03:04 PM UTC 24 Sep 18 09:03:06 PM UTC 24 46275189 ps
T47 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/3.spi_device_mem_parity.4253092604 Sep 18 09:03:04 PM UTC 24 Sep 18 09:03:07 PM UTC 24 64022342 ps
T31 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_rw.3005471727 Sep 18 09:03:26 PM UTC 24 Sep 18 09:03:29 PM UTC 24 37522481 ps
T49 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/2.spi_device_read_buffer_direct.3349518883 Sep 18 09:02:59 PM UTC 24 Sep 18 09:03:07 PM UTC 24 778077840 ps
T117 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_sts_read.197951252 Sep 18 09:03:05 PM UTC 24 Sep 18 09:03:08 PM UTC 24 1010476053 ps
T104 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/0.spi_device_intercept.2519255158 Sep 18 09:02:39 PM UTC 24 Sep 18 09:03:08 PM UTC 24 9666100409 ps
T63 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/2.spi_device_pass_cmd_filtering.2961944729 Sep 18 09:02:53 PM UTC 24 Sep 18 09:03:09 PM UTC 24 11658809219 ps
T48 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_rw.3744289877 Sep 18 09:03:06 PM UTC 24 Sep 18 09:03:10 PM UTC 24 212429098 ps
T45 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_all.2250352912 Sep 18 09:02:42 PM UTC 24 Sep 18 09:03:10 PM UTC 24 29524749607 ps
T105 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/0.spi_device_cfg_cmd.3343307130 Sep 18 09:02:40 PM UTC 24 Sep 18 09:03:11 PM UTC 24 24049993168 ps
T118 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_read_hw_reg.3543462412 Sep 18 09:03:05 PM UTC 24 Sep 18 09:03:11 PM UTC 24 931995777 ps
T66 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/3.spi_device_pass_addr_payload_swap.3216207815 Sep 18 09:03:08 PM UTC 24 Sep 18 09:03:13 PM UTC 24 1200853054 ps
T58 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/3.spi_device_pass_cmd_filtering.1466125813 Sep 18 09:03:07 PM UTC 24 Sep 18 09:03:15 PM UTC 24 2438555798 ps
T59 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/3.spi_device_intercept.3947535695 Sep 18 09:03:08 PM UTC 24 Sep 18 09:03:16 PM UTC 24 490866335 ps
T106 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/3.spi_device_cfg_cmd.738100949 Sep 18 09:03:10 PM UTC 24 Sep 18 09:03:18 PM UTC 24 4228913328 ps
T46 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_all.1880237632 Sep 18 09:03:05 PM UTC 24 Sep 18 09:03:19 PM UTC 24 2796285871 ps
T32 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/3.spi_device_sec_cm.1267121595 Sep 18 09:03:18 PM UTC 24 Sep 18 09:03:22 PM UTC 24 182682761 ps
T409 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/3.spi_device_alert_test.2911738104 Sep 18 09:03:20 PM UTC 24 Sep 18 09:03:22 PM UTC 24 43149154 ps
T179 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/3.spi_device_read_buffer_direct.150740712 Sep 18 09:03:12 PM UTC 24 Sep 18 09:03:22 PM UTC 24 2886119640 ps
T55 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_mode.903346222 Sep 18 09:03:11 PM UTC 24 Sep 18 09:03:23 PM UTC 24 6496633849 ps
T410 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/4.spi_device_csb_read.860520017 Sep 18 09:03:23 PM UTC 24 Sep 18 09:03:25 PM UTC 24 43685115 ps
T411 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/4.spi_device_mem_parity.1838772472 Sep 18 09:03:23 PM UTC 24 Sep 18 09:03:25 PM UTC 24 21998856 ps
T412 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_all.1670128607 Sep 18 09:03:24 PM UTC 24 Sep 18 09:03:26 PM UTC 24 59287460 ps
T60 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/3.spi_device_upload.704171673 Sep 18 09:03:09 PM UTC 24 Sep 18 09:03:27 PM UTC 24 4678935593 ps
T413 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_sts_read.2831136112 Sep 18 09:03:26 PM UTC 24 Sep 18 09:03:28 PM UTC 24 253964362 ps
T80 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_and_tpm.2034724453 Sep 18 09:02:47 PM UTC 24 Sep 18 09:03:29 PM UTC 24 1738370350 ps
T65 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_all.1205936852 Sep 18 09:02:59 PM UTC 24 Sep 18 09:03:31 PM UTC 24 1408571259 ps
T81 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_and_tpm_min_idle.2777863271 Sep 18 09:02:41 PM UTC 24 Sep 18 09:03:32 PM UTC 24 26244940338 ps
T203 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/4.spi_device_pass_addr_payload_swap.609965939 Sep 18 09:03:28 PM UTC 24 Sep 18 09:03:33 PM UTC 24 655123207 ps
T241 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/0.spi_device_mailbox.2253318072 Sep 18 09:02:39 PM UTC 24 Sep 18 09:03:33 PM UTC 24 21901122752 ps
T143 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/4.spi_device_intercept.1543169199 Sep 18 09:03:29 PM UTC 24 Sep 18 09:03:34 PM UTC 24 56319302 ps
T67 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/4.spi_device_pass_cmd_filtering.1820321594 Sep 18 09:03:27 PM UTC 24 Sep 18 09:03:38 PM UTC 24 4916774212 ps
T180 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/4.spi_device_read_buffer_direct.2031219357 Sep 18 09:03:35 PM UTC 24 Sep 18 09:03:41 PM UTC 24 149342679 ps
T223 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/4.spi_device_cfg_cmd.126315123 Sep 18 09:03:32 PM UTC 24 Sep 18 09:03:43 PM UTC 24 461599657 ps
T33 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/4.spi_device_stress_all.3400216054 Sep 18 09:03:42 PM UTC 24 Sep 18 09:03:45 PM UTC 24 56298379 ps
T82 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/4.spi_device_upload.1288407270 Sep 18 09:03:29 PM UTC 24 Sep 18 09:03:45 PM UTC 24 2098548290 ps
T34 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/2.spi_device_stress_all.3184170033 Sep 18 09:03:01 PM UTC 24 Sep 18 09:03:45 PM UTC 24 16809079042 ps
T35 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/4.spi_device_sec_cm.2527027490 Sep 18 09:03:43 PM UTC 24 Sep 18 09:03:46 PM UTC 24 118144026 ps
T197 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/4.spi_device_alert_test.1622667387 Sep 18 09:03:44 PM UTC 24 Sep 18 09:03:46 PM UTC 24 12465246 ps
T198 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/5.spi_device_csb_read.1772284842 Sep 18 09:03:45 PM UTC 24 Sep 18 09:03:47 PM UTC 24 45488979 ps
T199 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/5.spi_device_mem_parity.1850010664 Sep 18 09:03:46 PM UTC 24 Sep 18 09:03:49 PM UTC 24 397423624 ps
T200 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_sts_read.2223235235 Sep 18 09:03:47 PM UTC 24 Sep 18 09:03:49 PM UTC 24 10651058 ps
T181 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_mode.2634907089 Sep 18 09:03:33 PM UTC 24 Sep 18 09:03:52 PM UTC 24 5447826564 ps
T116 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_rw.3634937376 Sep 18 09:03:49 PM UTC 24 Sep 18 09:03:53 PM UTC 24 164416314 ps
T61 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/5.spi_device_pass_addr_payload_swap.4251303952 Sep 18 09:03:51 PM UTC 24 Sep 18 09:03:58 PM UTC 24 4236114547 ps
T75 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/5.spi_device_pass_cmd_filtering.440007716 Sep 18 09:03:50 PM UTC 24 Sep 18 09:03:58 PM UTC 24 330483582 ps
T51 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.96006768 Sep 18 09:03:00 PM UTC 24 Sep 18 09:04:02 PM UTC 24 5957151205 ps
T76 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_read_hw_reg.1503905395 Sep 18 09:03:24 PM UTC 24 Sep 18 09:04:03 PM UTC 24 7458067520 ps
T77 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/5.spi_device_cfg_cmd.3539671320 Sep 18 09:03:59 PM UTC 24 Sep 18 09:04:04 PM UTC 24 39057754 ps
T78 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/5.spi_device_intercept.3361635306 Sep 18 09:03:53 PM UTC 24 Sep 18 09:04:04 PM UTC 24 433661548 ps
T53 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_and_tpm.2855191793 Sep 18 09:03:39 PM UTC 24 Sep 18 09:04:05 PM UTC 24 917591339 ps
T79 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/5.spi_device_mailbox.90438254 Sep 18 09:03:54 PM UTC 24 Sep 18 09:04:06 PM UTC 24 3426242660 ps
T54 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_all.1939344330 Sep 18 09:02:40 PM UTC 24 Sep 18 09:04:08 PM UTC 24 3241052146 ps
T414 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/5.spi_device_alert_test.3674543819 Sep 18 09:04:07 PM UTC 24 Sep 18 09:04:09 PM UTC 24 14300308 ps
T52 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_mode_ignore_cmds.4277277970 Sep 18 09:03:11 PM UTC 24 Sep 18 09:04:09 PM UTC 24 3582883536 ps
T36 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/5.spi_device_stress_all.1387594928 Sep 18 09:04:07 PM UTC 24 Sep 18 09:04:10 PM UTC 24 82769430 ps
T415 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/6.spi_device_csb_read.3144916929 Sep 18 09:04:09 PM UTC 24 Sep 18 09:04:11 PM UTC 24 52288627 ps
T243 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/5.spi_device_upload.2536646680 Sep 18 09:03:54 PM UTC 24 Sep 18 09:04:12 PM UTC 24 2558130564 ps
T37 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/3.spi_device_stress_all.1887592235 Sep 18 09:03:17 PM UTC 24 Sep 18 09:04:12 PM UTC 24 6757067515 ps
T416 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_read_hw_reg.2323733550 Sep 18 09:03:46 PM UTC 24 Sep 18 09:04:13 PM UTC 24 14959538919 ps
T417 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/6.spi_device_mem_parity.3107458993 Sep 18 09:04:10 PM UTC 24 Sep 18 09:04:13 PM UTC 24 24829317 ps
T100 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_all.3089721401 Sep 18 09:03:35 PM UTC 24 Sep 18 09:04:13 PM UTC 24 10249560753 ps
T120 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/5.spi_device_read_buffer_direct.641623672 Sep 18 09:04:03 PM UTC 24 Sep 18 09:04:13 PM UTC 24 3225397941 ps
T418 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.2088056664 Sep 18 09:04:12 PM UTC 24 Sep 18 09:04:15 PM UTC 24 84946010 ps
T108 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_mode_ignore_cmds.3991029057 Sep 18 09:02:46 PM UTC 24 Sep 18 09:04:17 PM UTC 24 2617470664 ps
T407 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_rw.2106855329 Sep 18 09:04:13 PM UTC 24 Sep 18 09:04:17 PM UTC 24 58462903 ps
T206 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/6.spi_device_intercept.2305480201 Sep 18 09:04:13 PM UTC 24 Sep 18 09:04:19 PM UTC 24 190431910 ps
T312 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/6.spi_device_cfg_cmd.644535773 Sep 18 09:04:16 PM UTC 24 Sep 18 09:04:20 PM UTC 24 106562467 ps
T182 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_mode.1103283497 Sep 18 09:03:59 PM UTC 24 Sep 18 09:04:20 PM UTC 24 4442173632 ps
T119 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/6.spi_device_upload.3096064384 Sep 18 09:04:15 PM UTC 24 Sep 18 09:04:24 PM UTC 24 2307617251 ps
T68 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.1146998247 Sep 18 09:02:41 PM UTC 24 Sep 18 09:04:24 PM UTC 24 4626633486 ps
T391 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_all.2639378477 Sep 18 09:03:46 PM UTC 24 Sep 18 09:04:27 PM UTC 24 7936370949 ps
T38 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/6.spi_device_stress_all.1477958236 Sep 18 09:04:25 PM UTC 24 Sep 18 09:04:28 PM UTC 24 75340817 ps
T419 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/6.spi_device_alert_test.1864989954 Sep 18 09:04:27 PM UTC 24 Sep 18 09:04:29 PM UTC 24 22307836 ps
T420 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/7.spi_device_csb_read.3098923059 Sep 18 09:04:28 PM UTC 24 Sep 18 09:04:30 PM UTC 24 23096324 ps
T69 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/6.spi_device_pass_addr_payload_swap.3809420770 Sep 18 09:04:13 PM UTC 24 Sep 18 09:04:32 PM UTC 24 4662528119 ps
T183 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/6.spi_device_read_buffer_direct.2919538337 Sep 18 09:04:20 PM UTC 24 Sep 18 09:04:32 PM UTC 24 642662333 ps
T421 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mem_parity.3975320721 Sep 18 09:04:30 PM UTC 24 Sep 18 09:04:33 PM UTC 24 62373680 ps
T422 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_all.227679600 Sep 18 09:04:33 PM UTC 24 Sep 18 09:04:35 PM UTC 24 12740225 ps
T423 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.2829872419 Sep 18 09:04:33 PM UTC 24 Sep 18 09:04:35 PM UTC 24 29414956 ps
T424 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_read_hw_reg.1768078114 Sep 18 09:04:10 PM UTC 24 Sep 18 09:04:36 PM UTC 24 4098576287 ps
T305 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/6.spi_device_pass_cmd_filtering.214750186 Sep 18 09:04:13 PM UTC 24 Sep 18 09:04:37 PM UTC 24 45486835123 ps
T400 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_rw.3447958427 Sep 18 09:04:34 PM UTC 24 Sep 18 09:04:37 PM UTC 24 177084358 ps
T325 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/7.spi_device_intercept.928472164 Sep 18 09:04:37 PM UTC 24 Sep 18 09:04:43 PM UTC 24 448792395 ps
T306 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.2722012103 Sep 18 09:04:36 PM UTC 24 Sep 18 09:04:46 PM UTC 24 4762124268 ps
T123 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_mode_ignore_cmds.445038616 Sep 18 09:04:18 PM UTC 24 Sep 18 09:04:46 PM UTC 24 13904175792 ps
T70 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.2253041388 Sep 18 09:04:36 PM UTC 24 Sep 18 09:04:47 PM UTC 24 1782366868 ps
T425 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/7.spi_device_cfg_cmd.1643078666 Sep 18 09:04:44 PM UTC 24 Sep 18 09:04:48 PM UTC 24 70849086 ps
T292 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/7.spi_device_upload.2148763681 Sep 18 09:04:39 PM UTC 24 Sep 18 09:04:49 PM UTC 24 813903810 ps
T207 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_mode.665226369 Sep 18 09:02:46 PM UTC 24 Sep 18 09:04:51 PM UTC 24 11201002136 ps
T426 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.1856959559 Sep 18 09:04:31 PM UTC 24 Sep 18 09:04:51 PM UTC 24 13069398856 ps
T205 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_all.499519012 Sep 18 09:03:12 PM UTC 24 Sep 18 09:04:54 PM UTC 24 10850677736 ps
T109 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_mode_ignore_cmds.3982214454 Sep 18 09:04:01 PM UTC 24 Sep 18 09:04:56 PM UTC 24 8229003252 ps
T427 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/7.spi_device_alert_test.1255832400 Sep 18 09:04:55 PM UTC 24 Sep 18 09:04:57 PM UTC 24 29932480 ps
T428 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/8.spi_device_csb_read.3539833184 Sep 18 09:04:56 PM UTC 24 Sep 18 09:04:58 PM UTC 24 20748287 ps
T429 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mem_parity.1571684245 Sep 18 09:04:58 PM UTC 24 Sep 18 09:05:01 PM UTC 24 17682334 ps
T184 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode.3146808311 Sep 18 09:04:46 PM UTC 24 Sep 18 09:05:02 PM UTC 24 433189763 ps
T110 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_all.2953728871 Sep 18 09:04:03 PM UTC 24 Sep 18 09:05:04 PM UTC 24 2392466527 ps
T430 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_sts_read.2227161456 Sep 18 09:05:02 PM UTC 24 Sep 18 09:05:05 PM UTC 24 72110420 ps
T398 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_rw.4243707288 Sep 18 09:05:05 PM UTC 24 Sep 18 09:05:08 PM UTC 24 24712311 ps
T397 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_all.3009663223 Sep 18 09:04:10 PM UTC 24 Sep 18 09:05:09 PM UTC 24 21417029220 ps
T102 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_and_tpm_min_idle.2274808404 Sep 18 09:04:25 PM UTC 24 Sep 18 09:05:10 PM UTC 24 2653608525 ps
T185 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.1560280360 Sep 18 09:04:48 PM UTC 24 Sep 18 09:05:10 PM UTC 24 1817512039 ps
T334 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.1196660610 Sep 18 09:05:07 PM UTC 24 Sep 18 09:05:12 PM UTC 24 141651788 ps
T274 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_mode.2681833642 Sep 18 09:04:18 PM UTC 24 Sep 18 09:05:12 PM UTC 24 29825029372 ps
T244 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/2.spi_device_mailbox.3670580189 Sep 18 09:02:55 PM UTC 24 Sep 18 09:05:13 PM UTC 24 125782666006 ps
T431 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.376503916 Sep 18 09:04:59 PM UTC 24 Sep 18 09:05:14 PM UTC 24 4556944027 ps
T432 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/8.spi_device_cfg_cmd.563457597 Sep 18 09:05:11 PM UTC 24 Sep 18 09:05:15 PM UTC 24 123916367 ps
T433 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.1476036045 Sep 18 09:05:13 PM UTC 24 Sep 18 09:05:16 PM UTC 24 18617362 ps
T41 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/7.spi_device_stress_all.2137589078 Sep 18 09:04:52 PM UTC 24 Sep 18 09:05:18 PM UTC 24 3214936440 ps
T84 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_and_tpm_min_idle.2422154273 Sep 18 09:02:47 PM UTC 24 Sep 18 09:05:19 PM UTC 24 80770599532 ps
T91 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mailbox.1625373257 Sep 18 09:05:10 PM UTC 24 Sep 18 09:05:20 PM UTC 24 502668160 ps
T92 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.1891107726 Sep 18 09:05:14 PM UTC 24 Sep 18 09:05:21 PM UTC 24 340758333 ps
T93 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/8.spi_device_alert_test.442097772 Sep 18 09:05:20 PM UTC 24 Sep 18 09:05:22 PM UTC 24 14910016 ps
T94 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/8.spi_device_intercept.3158335604 Sep 18 09:05:09 PM UTC 24 Sep 18 09:05:22 PM UTC 24 2471179872 ps
T95 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/9.spi_device_csb_read.1394135993 Sep 18 09:05:21 PM UTC 24 Sep 18 09:05:23 PM UTC 24 29340932 ps
T96 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mem_parity.2852609342 Sep 18 09:05:22 PM UTC 24 Sep 18 09:05:24 PM UTC 24 154775929 ps
T97 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/8.spi_device_upload.2028152309 Sep 18 09:05:11 PM UTC 24 Sep 18 09:05:26 PM UTC 24 396432241 ps
T98 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.2188126886 Sep 18 09:05:24 PM UTC 24 Sep 18 09:05:26 PM UTC 24 43200478 ps
T99 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_rw.2682567745 Sep 18 09:05:25 PM UTC 24 Sep 18 09:05:27 PM UTC 24 27217699 ps
T71 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode_ignore_cmds.3408312107 Sep 18 09:04:46 PM UTC 24 Sep 18 09:05:29 PM UTC 24 3680470335 ps
T434 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.2201054481 Sep 18 09:05:23 PM UTC 24 Sep 18 09:05:31 PM UTC 24 2915241394 ps
T435 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.118569929 Sep 18 09:05:27 PM UTC 24 Sep 18 09:05:32 PM UTC 24 49959660 ps
T259 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_and_tpm.3877467391 Sep 18 09:03:14 PM UTC 24 Sep 18 09:05:32 PM UTC 24 57899567657 ps
T267 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.949690714 Sep 18 09:05:26 PM UTC 24 Sep 18 09:05:32 PM UTC 24 205644040 ps
T277 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/9.spi_device_intercept.2282961502 Sep 18 09:05:28 PM UTC 24 Sep 18 09:05:35 PM UTC 24 409458301 ps
T288 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode.2493186213 Sep 18 09:05:12 PM UTC 24 Sep 18 09:05:36 PM UTC 24 6904705469 ps
T394 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_all.2511257056 Sep 18 09:05:23 PM UTC 24 Sep 18 09:05:37 PM UTC 24 2821950958 ps
T436 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/9.spi_device_cfg_cmd.3062152670 Sep 18 09:05:33 PM UTC 24 Sep 18 09:05:37 PM UTC 24 55217836 ps
T72 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_all.3103834046 Sep 18 09:02:47 PM UTC 24 Sep 18 09:05:38 PM UTC 24 35154450234 ps
T437 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/9.spi_device_alert_test.4009542470 Sep 18 09:05:39 PM UTC 24 Sep 18 09:05:41 PM UTC 24 30411114 ps
T438 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.505070112 Sep 18 09:05:34 PM UTC 24 Sep 18 09:05:42 PM UTC 24 351426745 ps
T121 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_mode_ignore_cmds.3594388800 Sep 18 09:03:34 PM UTC 24 Sep 18 09:05:44 PM UTC 24 54743290256 ps
T399 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_all.1217816231 Sep 18 09:05:02 PM UTC 24 Sep 18 09:05:44 PM UTC 24 5836612199 ps
T73 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_all.1944068178 Sep 18 09:04:21 PM UTC 24 Sep 18 09:05:44 PM UTC 24 14339860019 ps
T386 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode.186767090 Sep 18 09:05:33 PM UTC 24 Sep 18 09:05:44 PM UTC 24 2518768623 ps
T439 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/10.spi_device_csb_read.2986187882 Sep 18 09:05:42 PM UTC 24 Sep 18 09:05:44 PM UTC 24 23406070 ps
T318 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/9.spi_device_upload.1617337093 Sep 18 09:05:32 PM UTC 24 Sep 18 09:05:45 PM UTC 24 1750088564 ps
T440 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/10.spi_device_mem_parity.444733573 Sep 18 09:05:43 PM UTC 24 Sep 18 09:05:46 PM UTC 24 26960895 ps
T441 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_sts_read.4038303991 Sep 18 09:05:45 PM UTC 24 Sep 18 09:05:47 PM UTC 24 140909440 ps
T442 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_rw.1985758881 Sep 18 09:05:45 PM UTC 24 Sep 18 09:05:48 PM UTC 24 83443524 ps
T443 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/3.spi_device_mailbox.693771923 Sep 18 09:03:09 PM UTC 24 Sep 18 09:05:51 PM UTC 24 61071250753 ps
T444 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/10.spi_device_mailbox.3696977945 Sep 18 09:05:47 PM UTC 24 Sep 18 09:05:51 PM UTC 24 74679403 ps
T270 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/10.spi_device_pass_cmd_filtering.3048103918 Sep 18 09:05:45 PM UTC 24 Sep 18 09:05:54 PM UTC 24 298161379 ps
T300 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/10.spi_device_cfg_cmd.383920716 Sep 18 09:05:49 PM UTC 24 Sep 18 09:05:54 PM UTC 24 239147882 ps
T204 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.3958699247 Sep 18 09:05:05 PM UTC 24 Sep 18 09:05:54 PM UTC 24 101552731148 ps
T74 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/10.spi_device_pass_addr_payload_swap.174214146 Sep 18 09:05:45 PM UTC 24 Sep 18 09:05:56 PM UTC 24 696203729 ps
T445 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_all.684711651 Sep 18 09:05:55 PM UTC 24 Sep 18 09:05:57 PM UTC 24 12716279 ps
T297 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/10.spi_device_upload.3966029161 Sep 18 09:05:48 PM UTC 24 Sep 18 09:05:57 PM UTC 24 1023010257 ps
T446 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mailbox.1491278335 Sep 18 09:04:38 PM UTC 24 Sep 18 09:05:58 PM UTC 24 20668306391 ps
T296 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/4.spi_device_mailbox.1071040607 Sep 18 09:03:29 PM UTC 24 Sep 18 09:06:00 PM UTC 24 12351250852 ps
T447 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/10.spi_device_read_buffer_direct.1861983373 Sep 18 09:05:52 PM UTC 24 Sep 18 09:06:00 PM UTC 24 252347417 ps
T448 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/11.spi_device_csb_read.458854039 Sep 18 09:05:58 PM UTC 24 Sep 18 09:06:00 PM UTC 24 25983825 ps
T449 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/10.spi_device_alert_test.625024681 Sep 18 09:05:58 PM UTC 24 Sep 18 09:06:00 PM UTC 24 11293330 ps
T450 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/11.spi_device_mem_parity.2252883977 Sep 18 09:05:59 PM UTC 24 Sep 18 09:06:02 PM UTC 24 43186629 ps
T451 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_mode.3080968527 Sep 18 09:05:51 PM UTC 24 Sep 18 09:06:03 PM UTC 24 637393328 ps
T403 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_rw.2103790536 Sep 18 09:06:02 PM UTC 24 Sep 18 09:06:04 PM UTC 24 54009751 ps
T452 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_sts_read.1822392159 Sep 18 09:06:02 PM UTC 24 Sep 18 09:06:04 PM UTC 24 37648061 ps
T264 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/6.spi_device_mailbox.928502231 Sep 18 09:04:13 PM UTC 24 Sep 18 09:06:07 PM UTC 24 50365403225 ps
T453 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/11.spi_device_pass_addr_payload_swap.2804792970 Sep 18 09:06:04 PM UTC 24 Sep 18 09:06:08 PM UTC 24 73751236 ps
T393 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_all.3387268312 Sep 18 09:05:45 PM UTC 24 Sep 18 09:06:08 PM UTC 24 1568536896 ps
T265 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/10.spi_device_intercept.1435105267 Sep 18 09:05:46 PM UTC 24 Sep 18 09:06:09 PM UTC 24 3340394058 ps
T222 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/11.spi_device_upload.2864410800 Sep 18 09:06:07 PM UTC 24 Sep 18 09:06:11 PM UTC 24 50446370 ps
T454 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_read_hw_reg.3456089034 Sep 18 09:06:01 PM UTC 24 Sep 18 09:06:12 PM UTC 24 3587474697 ps
T302 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mailbox.1042775386 Sep 18 09:05:30 PM UTC 24 Sep 18 09:06:14 PM UTC 24 2272751600 ps
T245 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/11.spi_device_intercept.323369195 Sep 18 09:06:05 PM UTC 24 Sep 18 09:06:14 PM UTC 24 1366879470 ps
T455 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_mode.2845241070 Sep 18 09:06:09 PM UTC 24 Sep 18 09:06:16 PM UTC 24 759451671 ps
T103 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_and_tpm.3335524179 Sep 18 09:04:21 PM UTC 24 Sep 18 09:06:16 PM UTC 24 43567196764 ps
T456 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/11.spi_device_alert_test.1557703002 Sep 18 09:06:16 PM UTC 24 Sep 18 09:06:18 PM UTC 24 26082348 ps
T457 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_read_hw_reg.3023980728 Sep 18 09:05:45 PM UTC 24 Sep 18 09:06:18 PM UTC 24 24397250378 ps
T458 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/12.spi_device_csb_read.2099801993 Sep 18 09:06:17 PM UTC 24 Sep 18 09:06:20 PM UTC 24 15973886 ps
T459 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/12.spi_device_mem_parity.3355044193 Sep 18 09:06:17 PM UTC 24 Sep 18 09:06:20 PM UTC 24 270568349 ps
T401 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_all.2638684256 Sep 18 09:06:01 PM UTC 24 Sep 18 09:06:21 PM UTC 24 3801529357 ps
T221 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_mode_ignore_cmds.2980212606 Sep 18 09:05:52 PM UTC 24 Sep 18 09:06:21 PM UTC 24 2052224414 ps
T460 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/11.spi_device_read_buffer_direct.4276209803 Sep 18 09:06:09 PM UTC 24 Sep 18 09:06:23 PM UTC 24 5460729177 ps
T461 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_sts_read.451720155 Sep 18 09:06:20 PM UTC 24 Sep 18 09:06:24 PM UTC 24 746924150 ps
T313 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/11.spi_device_pass_cmd_filtering.1433318873 Sep 18 09:06:03 PM UTC 24 Sep 18 09:06:24 PM UTC 24 3074599267 ps
T462 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_rw.4180431703 Sep 18 09:06:21 PM UTC 24 Sep 18 09:06:27 PM UTC 24 280210546 ps
T202 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.512763937 Sep 18 09:05:16 PM UTC 24 Sep 18 09:06:27 PM UTC 24 22247384315 ps
T321 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/11.spi_device_cfg_cmd.2355792880 Sep 18 09:06:08 PM UTC 24 Sep 18 09:06:29 PM UTC 24 1502733021 ps
T463 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/12.spi_device_intercept.4060478232 Sep 18 09:06:25 PM UTC 24 Sep 18 09:06:29 PM UTC 24 673774123 ps
T464 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_read_hw_reg.959143198 Sep 18 09:06:19 PM UTC 24 Sep 18 09:06:31 PM UTC 24 741427290 ps
T465 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_mode_ignore_cmds.274687129 Sep 18 09:06:29 PM UTC 24 Sep 18 09:06:31 PM UTC 24 17825870 ps
T237 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.664878077 Sep 18 09:04:52 PM UTC 24 Sep 18 09:06:35 PM UTC 24 125676603087 ps
T271 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/11.spi_device_mailbox.3149669991 Sep 18 09:06:05 PM UTC 24 Sep 18 09:06:37 PM UTC 24 3343328509 ps
T309 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/12.spi_device_mailbox.114211872 Sep 18 09:06:25 PM UTC 24 Sep 18 09:06:38 PM UTC 24 5586921847 ps
T230 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/12.spi_device_pass_cmd_filtering.2506807661 Sep 18 09:06:23 PM UTC 24 Sep 18 09:06:39 PM UTC 24 1179649989 ps
T352 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/12.spi_device_cfg_cmd.269775738 Sep 18 09:06:28 PM UTC 24 Sep 18 09:06:40 PM UTC 24 2426165868 ps
T466 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/12.spi_device_alert_test.763720441 Sep 18 09:06:38 PM UTC 24 Sep 18 09:06:42 PM UTC 24 60871188 ps
T190 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/12.spi_device_stress_all.1322925768 Sep 18 09:06:38 PM UTC 24 Sep 18 09:06:42 PM UTC 24 293338305 ps
T467 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/13.spi_device_csb_read.3292740146 Sep 18 09:06:41 PM UTC 24 Sep 18 09:06:43 PM UTC 24 16630316 ps
T468 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/13.spi_device_mem_parity.2707763663 Sep 18 09:06:41 PM UTC 24 Sep 18 09:06:43 PM UTC 24 23515328 ps
T122 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_mode_ignore_cmds.3597707813 Sep 18 09:02:40 PM UTC 24 Sep 18 09:06:44 PM UTC 24 46072129094 ps
T280 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/12.spi_device_pass_addr_payload_swap.1484843296 Sep 18 09:06:23 PM UTC 24 Sep 18 09:06:45 PM UTC 24 18891884126 ps
T469 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_sts_read.880745751 Sep 18 09:06:44 PM UTC 24 Sep 18 09:06:46 PM UTC 24 27639545 ps
T470 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_all.1134872499 Sep 18 09:06:43 PM UTC 24 Sep 18 09:06:46 PM UTC 24 116906571 ps
T471 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_rw.733201179 Sep 18 09:06:44 PM UTC 24 Sep 18 09:06:47 PM UTC 24 196943168 ps
T472 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_mode.375447468 Sep 18 09:06:28 PM UTC 24 Sep 18 09:06:47 PM UTC 24 1847129208 ps
T473 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/12.spi_device_read_buffer_direct.3789412877 Sep 18 09:06:30 PM UTC 24 Sep 18 09:06:50 PM UTC 24 2982786073 ps
T242 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_and_tpm_min_idle.3843414745 Sep 18 09:03:16 PM UTC 24 Sep 18 09:06:51 PM UTC 24 276413948704 ps
T338 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/13.spi_device_pass_addr_payload_swap.1958039199 Sep 18 09:06:45 PM UTC 24 Sep 18 09:06:53 PM UTC 24 989806765 ps
T315 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/13.spi_device_intercept.2523790015 Sep 18 09:06:47 PM UTC 24 Sep 18 09:06:56 PM UTC 24 758886819 ps
T234 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/13.spi_device_pass_cmd_filtering.853378535 Sep 18 09:06:45 PM UTC 24 Sep 18 09:06:56 PM UTC 24 1009758015 ps
T474 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/12.spi_device_upload.3687466341 Sep 18 09:06:25 PM UTC 24 Sep 18 09:06:58 PM UTC 24 10655859800 ps
T311 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/13.spi_device_cfg_cmd.1248758180 Sep 18 09:06:47 PM UTC 24 Sep 18 09:06:59 PM UTC 24 1092820715 ps
T402 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_all.418193662 Sep 18 09:06:19 PM UTC 24 Sep 18 09:07:01 PM UTC 24 2825712624 ps
T475 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/13.spi_device_read_buffer_direct.2234263593 Sep 18 09:06:54 PM UTC 24 Sep 18 09:07:02 PM UTC 24 733942506 ps
T476 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/13.spi_device_alert_test.1158491593 Sep 18 09:07:00 PM UTC 24 Sep 18 09:07:02 PM UTC 24 100232045 ps
T477 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/14.spi_device_csb_read.827530283 Sep 18 09:07:02 PM UTC 24 Sep 18 09:07:04 PM UTC 24 72501002 ps