Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	32607	1			T15	2		T16	2		T17	2
auto[SpiFlashAddrCfg]	7137	1			T15	4		T17	2		T21	2
auto[SpiFlashAddr3b]	8773	1			T13	3		T15	4		T17	12
auto[SpiFlashAddr4b]	7033	1			T13	1		T15	4		T16	2

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32668

1

T13

4

T15

14

T17

24

auto[1]

22882

1

T16

4

T23

16

T64

16

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29467

1

T13

4

T15

8

T16

4

auto[1]

26083

1

T15

6

T17

6

T21

2

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	37127	1			T15	4		T16	2		T17	8
values[1]	1016	1			T50	3		T60	4		T51	3
values[2]	1337	1			T13	1		T23	2		T24	4
values[3]	1390	1			T62	2		T64	6		T63	4
values[4]	1337	1			T23	2		T57	4		T51	2
values[5]	1414	1			T50	1		T66	2		T65	2
values[6]	1305	1			T13	3		T24	4		T62	2
values[7]	1409	1			T15	4		T16	2		T63	2
values[8]	9215	1			T15	6		T17	16		T23	8

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27240

1

T15

14

T16

4

T17

24

auto[1]

28310

1

T13

4

T50

4

T55

7

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

52482

1

T13

4

T15

14

T16

4

write

3068

1

T17

2

T24

4

T58

2

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

18091

1

T13

4

T15

10

T17

14

valids[0x1]

37459

1

T15

4

T16

4

T17

10

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1428	1			T15	2		T23	2		T57	4
internal_process_ops[0x5a]	1466	1			T23	2		T24	4		T62	2
internal_process_ops[0x05]	19490	1			T16	2		T24	73		T56	60
internal_process_ops[0x35]	1509	1			T24	2		T62	2		T64	2
internal_process_ops[0x15]	1572	1			T23	2		T58	2		T59	2
internal_process_ops[0x03]	959	1			T16	2		T21	2		T24	2
internal_process_ops[0x0b]	1005	1			T17	2		T56	2		T64	2
internal_process_ops[0x3b]	888	1			T57	4		T62	2		T82	6
internal_process_ops[0x6b]	940	1			T13	1		T15	2		T57	2
internal_process_ops[0xbb]	941	1			T17	2		T59	4		T65	2
internal_process_ops[0xeb]	960	1			T13	3		T17	2		T104	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

54025

1

T13

4

T15

14

T16

4

auto[1]

1525

1

T65

1

T61

2

T51

4

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

53290

1

T13

4

T15

14

T16

4

auto[1]

2260

1

T24

4

T56

2

T65

3

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9976

1

T15

2

T22

6

T24

77

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

4955

1

T16

2

T23

6

T64

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1832

1

T15

4

T17

2

T21

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1595

1

T23

4

T66

2

T203

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2258

1

T15

4

T17

12

T24

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1903

1

T23

6

T64

6

T66

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1796

1

T15

4

T17

8

T24

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1566

1

T16

2

T64

8

T66

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

135

1

T17

2

T58

2

T59

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

78

1

T51

3

T68

1

T72

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

71

1

T71

1

T72

4

T73

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

70

1

T51

1

T69

2

T72

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

103

1

T51

1

T71

2

T72

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

85

1

T65

1

T52

1

T68

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

76

1

T52

1

T68

5

T73

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

92

1

T108

1

T70

2

T72

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

101

1

T119

4

T73

1

T204

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

77

1

T52

1

T108

1

T72

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

73

1

T108

4

T68

1

T72

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

75

1

T68

3

T71

1

T74

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

94

1

T24

4

T108

1

T68

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

69

1

T52

1

T73

1

T122

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

69

1

T51

2

T68

1

T72

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

91

1

T61

2

T68

1

T70

4

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10199

1

T53

10

T54

658

T37

72

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6700

1

T53

6

T54

52

T37

23

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1551

1

T50

3

T55

2

T181

1

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1435

1

T53

4

T54

20

T37

5

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1959

1

T13

3

T55

2

T53

3

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1826

1

T53

1

T54

25

T37

11

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1505

1

T13

1

T50

1

T55

3

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1426

1

T53

4

T54

19

T37

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

103

1

T54

3

T109

1

T110

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

106

1

T54

1

T37

2

T109

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

114

1

T37

1

T100

1

T123

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

100

1

T53

2

T109

4

T110

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

85

1

T100

1

T109

2

T110

4

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

91

1

T54

3

T37

1

T100

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

95

1

T54

4

T37

1

T110

4

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

97

1

T123

3

T205

1

T110

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

112

1

T53

2

T54

4

T100

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

144

1

T54

2

T37

3

T205

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

119

1

T54

6

T37

3

T100

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

126

1

T123

4

T205

1

T41

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

101

1

T54

2

T37

2

T205

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

108

1

T54

2

T37

1

T205

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

92

1

T205

1

T109

4

T110

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

116

1

T54

4

T205

1

T109

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3248	1			T15	2		T17	2		T22	6
auto[0]	values[0]	valids[0x1]	14202	1			T15	2		T16	2		T17	6
auto[0]	values[1]	valids[0x1]	509	1			T60	4		T51	3		T52	3
auto[0]	values[2]	valids[0x0]	428	1			T65	3		T51	3		T52	4
auto[0]	values[2]	valids[0x1]	264	1			T23	2		T24	4		T65	1
auto[0]	values[3]	valids[0x0]	511	1			T62	2		T64	6		T60	2
auto[0]	values[3]	valids[0x1]	257	1			T63	4		T65	3		T203	2
auto[0]	values[4]	valids[0x0]	468	1			T57	4		T51	2		T52	4
auto[0]	values[4]	valids[0x1]	215	1			T23	2		T108	1		T206	2
auto[0]	values[5]	valids[0x0]	419	1			T66	2		T65	1		T82	2
auto[0]	values[5]	valids[0x1]	280	1			T65	1		T51	1		T52	4
auto[0]	values[6]	valids[0x0]	437	1			T24	4		T60	6		T203	2
auto[0]	values[6]	valids[0x1]	227	1			T62	2		T104	2		T75	2
auto[0]	values[7]	valids[0x0]	478	1			T15	4		T65	3		T51	3
auto[0]	values[7]	valids[0x1]	310	1			T16	2		T63	2		T65	1
auto[0]	values[8]	valids[0x0]	3194	1			T15	4		T17	12		T23	4
auto[0]	values[8]	valids[0x1]	1793	1			T15	2		T17	4		T23	4
auto[1]	values[0]	valids[0x0]	4044	1			T53	10		T54	48		T37	41
auto[1]	values[0]	valids[0x1]	15633	1			T53	11		T54	716		T37	74
auto[1]	values[1]	valids[0x1]	507	1			T50	3		T53	1		T54	10
auto[1]	values[2]	valids[0x0]	379	1			T13	1		T54	7		T37	4
auto[1]	values[2]	valids[0x1]	266	1			T54	8		T37	3		T100	1
auto[1]	values[3]	valids[0x0]	389	1			T181	1		T54	10		T37	2
auto[1]	values[3]	valids[0x1]	233	1			T54	8		T182	3		T205	2
auto[1]	values[4]	valids[0x0]	407	1			T53	1		T54	4		T37	4
auto[1]	values[4]	valids[0x1]	247	1			T54	6		T100	2		T207	2
auto[1]	values[5]	valids[0x0]	414	1			T50	1		T54	2		T37	3
auto[1]	values[5]	valids[0x1]	301	1			T53	5		T54	4		T37	1
auto[1]	values[6]	valids[0x0]	374	1			T13	3		T53	3		T54	1
auto[1]	values[6]	valids[0x1]	267	1			T55	2		T53	1		T54	4
auto[1]	values[7]	valids[0x0]	383	1			T53	3		T54	6		T37	2
auto[1]	values[7]	valids[0x1]	238	1			T53	2		T54	3		T100	1
auto[1]	values[8]	valids[0x0]	2518	1			T55	5		T53	4		T54	28
auto[1]	values[8]	valids[0x1]	1710	1			T181	1		T54	16		T37	12