Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3336121

1

T13

121

T15

1

T16

1

auto[1]

29422

1

T24

73

T56

60

T65

104

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1085758

1

T13

121

T15

1

T16

1

auto[1]

2279785

1

T24

585

T56

60

T62

10314

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	703824	1			T13	2		T15	1		T16	1
auto[524288:1048575]	395059	1			T13	96		T21	95		T22	207
auto[1048576:1572863]	389651	1			T21	61		T57	93		T83	2
auto[1572864:2097151]	441623	1			T13	23		T21	370		T22	246
auto[2097152:2621439]	319901	1			T21	44		T22	236		T57	3
auto[2621440:3145727]	379215	1			T21	386		T22	132		T57	2
auto[3145728:3670015]	361519	1			T21	151		T57	3		T101	14
auto[3670016:4194303]	374751	1			T21	138		T22	47		T101	4

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2312015

1

T13

6

T15

1

T16

1

auto[1]

1053528

1

T13

115

T21

1445

T22

597

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2917800

1

T13

121

T15

1

T16

1

auto[1]

447743

1

T101

2732

T65

992

T51

556

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	263420	1			T13	2		T15	1		T16	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	386387	1			T24	516		T56	2		T62	10314
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	138493	1			T13	96		T21	95		T22	207
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	209757	1			T104	513		T51	2804		T54	513
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	101319	1			T21	61		T57	93		T83	2
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	232184	1			T78	148		T53	1		T54	3202
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	108142	1			T13	23		T21	370		T22	246
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	255282	1			T104	1		T65	128		T51	256
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	125420	1			T21	44		T22	236		T57	3
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	156961	1			T54	2632		T52	256		T37	1
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	122896	1			T21	386		T22	132		T57	2
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	184973	1			T65	1		T54	4025		T37	1
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	97847	1			T21	151		T57	3		T101	14
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	199330	1			T51	129		T78	9		T54	5193
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	114285	1			T21	138		T22	47		T101	3
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	196647	1			T51	7		T54	2563		T52	256
auto[0]	auto[1]	auto[0:524287]	auto[0]	2311	1			T101	694		T65	2		T53	2
auto[0]	auto[1]	auto[0:524287]	auto[1]	47207	1			T65	1		T68	1		T71	3
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	793	1			T51	1		T54	6		T37	6
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	42239	1			T54	769		T37	2		T205	257
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	604	1			T101	2		T65	2		T100	2
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	52138	1			T65	512		T100	1025		T108	2941
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	1388	1			T101	684		T65	2		T51	3
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	72951	1			T65	1		T51	512		T54	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	959	1			T54	7		T68	1		T110	3
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	33499	1			T65	410		T54	1097		T110	257
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	1937	1			T101	1351		T54	1		T52	13
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	66085	1			T52	2699		T37	811		T68	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	1017	1			T51	3		T37	4		T108	15
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	58825	1			T37	346		T108	604		T221	128
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	994	1			T101	1		T51	5		T108	5
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	59831	1			T51	2		T108	5		T71	256
auto[1]	auto[0]	auto[0:524287]	auto[0]	493	1			T24	4		T56	2		T82	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	3623	1			T24	69		T56	58		T82	46
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	366	1			T54	1		T52	3		T100	2
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2572	1			T54	25		T100	42		T110	4
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	393	1			T53	1		T54	1		T100	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2651	1			T54	5		T100	4		T205	14
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	432	1			T54	2		T37	2		T68	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2605	1			T54	55		T37	13		T68	47
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	371	1			T54	4		T52	5		T37	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1918	1			T54	60		T37	8		T68	82
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	375	1			T65	1		T52	10		T37	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2524	1			T65	41		T68	46		T205	64
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	452	1			T51	1		T54	2		T52	5
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	3418	1			T51	2		T54	86		T108	249
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	372	1			T51	2		T54	8		T37	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1892	1			T51	13		T54	185		T37	1
auto[1]	auto[1]	auto[0:524287]	auto[0]	64	1			T65	1		T68	1		T72	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	319	1			T65	9		T68	50		T72	27
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	101	1			T54	1		T37	2		T205	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	738	1			T54	19		T37	5		T205	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	88	1			T73	2		T242	1		T281	4
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	274	1			T73	37		T281	2		T247	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	107	1			T65	1		T54	1		T100	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	716	1			T65	51		T54	14		T100	12
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	66	1			T54	2		T110	1		T102	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	707	1			T54	52		T110	23		T102	26
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	79	1			T68	1		T71	3		T221	12
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	346	1			T68	29		T294	2		T295	4
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	96	1			T123	8		T109	14		T231	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	534	1			T123	128		T231	3		T191	2
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	78	1			T51	2		T235	1		T247	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	652	1			T51	28		T247	23		T224	70

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1846297	1			T13	6		T15	1		T16	1
auto[0]	auto[0]	auto[1]	1047046	1			T13	115		T21	1445		T22	597
auto[0]	auto[1]	auto[0]	436926	1			T101	48		T65	930		T51	525
auto[0]	auto[1]	auto[1]	5852	1			T101	2684		T51	1		T54	3
auto[1]	auto[0]	auto[0]	23949	1			T24	70		T56	60		T65	42
auto[1]	auto[0]	auto[1]	508	1			T24	3		T51	1		T54	1
auto[1]	auto[1]	auto[0]	4843	1			T65	62		T51	29		T54	89
auto[1]	auto[1]	auto[1]	122	1			T51	1		T123	2		T205	1