Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2835363	1			T1	1		T2	1		T3	1
all_pins[1]	2835363	1			T1	1		T2	1		T3	1
all_pins[2]	2835363	1			T1	1		T2	1		T3	1
all_pins[3]	2835363	1			T1	1		T2	1		T3	1
all_pins[4]	2835363	1			T1	1		T2	1		T3	1
all_pins[5]	2835363	1			T1	1		T2	1		T3	1
all_pins[6]	2835363	1			T1	1		T2	1		T3	1
all_pins[7]	2835363	1			T1	1		T2	1		T3	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	22652921	1			T1	8		T2	8		T3	8
values[0x1]	29983	1			T33	36		T34	29		T36	48
transitions[0x0=>0x1]	29353	1			T33	25		T34	19		T36	35
transitions[0x1=>0x0]	29365	1			T33	25		T34	19		T36	35

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2835181	1			T1	1		T2	1		T3	1
all_pins[0]	values[0x1]	182	1			T33	3		T34	3		T36	7
all_pins[0]	transitions[0x0=>0x1]	135	1			T33	2		T34	2		T36	7
all_pins[0]	transitions[0x1=>0x0]	518	1			T33	6		T34	1		T36	3
all_pins[1]	values[0x0]	2834798	1			T1	1		T2	1		T3	1
all_pins[1]	values[0x1]	565	1			T33	7		T34	2		T36	3
all_pins[1]	transitions[0x0=>0x1]	417	1			T33	6		T34	1		T36	2
all_pins[1]	transitions[0x1=>0x0]	169	1			T33	3		T34	4		T36	9
all_pins[2]	values[0x0]	2835046	1			T1	1		T2	1		T3	1
all_pins[2]	values[0x1]	317	1			T33	4		T34	5		T36	10
all_pins[2]	transitions[0x0=>0x1]	262	1			T33	2		T34	1		T36	7
all_pins[2]	transitions[0x1=>0x0]	132	1			T33	2		T34	4		T37	4
all_pins[3]	values[0x0]	2835176	1			T1	1		T2	1		T3	1
all_pins[3]	values[0x1]	187	1			T33	4		T34	8		T36	3
all_pins[3]	transitions[0x0=>0x1]	153	1			T33	4		T34	7		T36	2
all_pins[3]	transitions[0x1=>0x0]	152	1			T33	2		T34	1		T36	3
all_pins[4]	values[0x0]	2835177	1			T1	1		T2	1		T3	1
all_pins[4]	values[0x1]	186	1			T33	2		T34	2		T36	4
all_pins[4]	transitions[0x0=>0x1]	154	1			T33	2		T34	2		T36	2
all_pins[4]	transitions[0x1=>0x0]	888	1			T33	5		T34	1		T36	5
all_pins[5]	values[0x0]	2834443	1			T1	1		T2	1		T3	1
all_pins[5]	values[0x1]	920	1			T33	5		T34	1		T36	7
all_pins[5]	transitions[0x0=>0x1]	714	1			T33	3		T36	5		T37	2
all_pins[5]	transitions[0x1=>0x0]	27208	1			T33	2		T34	3		T36	6
all_pins[6]	values[0x0]	2807949	1			T1	1		T2	1		T3	1
all_pins[6]	values[0x1]	27414	1			T33	4		T34	4		T36	8
all_pins[6]	transitions[0x0=>0x1]	27353	1			T33	1		T34	2		T36	6
all_pins[6]	transitions[0x1=>0x0]	151	1			T33	4		T34	2		T36	4
all_pins[7]	values[0x0]	2835151	1			T1	1		T2	1		T3	1
all_pins[7]	values[0x1]	212	1			T33	7		T34	4		T36	6
all_pins[7]	transitions[0x0=>0x1]	165	1			T33	5		T34	4		T36	4
all_pins[7]	transitions[0x1=>0x0]	147	1			T33	1		T34	3		T36	5