Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16604

1

T15

14

T17

24

T21

2

auto[1]

10636

1

T16

4

T23

16

T64

16

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4130	1			T23	16		T60	24		T51	33
values[1]	3331	1			T21	2		T223	6		T51	50
values[2]	3136	1			T24	91		T101	20		T203	4
values[3]	2802	1			T51	35		T52	20		T108	20
values[4]	3059	1			T15	14		T57	10		T56	64
values[5]	4133	1			T17	24		T62	14		T63	18
values[6]	3342	1			T16	4		T105	6		T59	10
values[7]	3307	1			T22	6		T104	10		T66	14

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3344	1			T15	14		T16	4		T57	10
values[1]	4355	1			T65	20		T67	4		T51	20
values[2]	3255	1			T22	6		T119	136		T68	351
values[3]	3577	1			T23	16		T56	64		T106	4
values[4]	3550	1			T21	2		T24	91		T101	20
values[5]	2737	1			T64	16		T104	10		T60	24
values[6]	2923	1			T17	24		T62	14		T65	124
values[7]	3499	1			T105	6		T75	14		T51	20

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	240	1			T271	22		T111	8		T231	20
auto[0]	values[0]	values[1]	217	1			T68	9		T72	15		T296	8
auto[0]	values[0]	values[2]	415	1			T68	149		T297	2		T298	16
auto[0]	values[0]	values[3]	337	1			T51	9		T94	16		T111	8
auto[0]	values[0]	values[4]	377	1			T243	24		T72	10		T103	14
auto[0]	values[0]	values[5]	189	1			T60	24		T68	12		T71	11
auto[0]	values[0]	values[6]	263	1			T122	25		T299	16		T168	27
auto[0]	values[0]	values[7]	373	1			T52	13		T68	63		T73	24
auto[0]	values[1]	values[0]	363	1			T223	6		T51	41		T78	8
auto[0]	values[1]	values[1]	406	1			T73	51		T300	18		T202	16
auto[0]	values[1]	values[2]	237	1			T111	13		T231	10		T301	24
auto[0]	values[1]	values[3]	206	1			T111	7		T256	15		T225	15
auto[0]	values[1]	values[4]	223	1			T21	2		T68	44		T111	9
auto[0]	values[1]	values[5]	309	1			T108	13		T68	23		T235	8
auto[0]	values[1]	values[6]	222	1			T68	15		T302	8		T111	32
auto[0]	values[1]	values[7]	130	1			T77	2		T71	15		T72	9
auto[0]	values[2]	values[0]	177	1			T225	8		T42	15		T194	12
auto[0]	values[2]	values[1]	248	1			T285	47		T303	4		T226	12
auto[0]	values[2]	values[2]	325	1			T72	68		T73	46		T270	10
auto[0]	values[2]	values[3]	88	1			T72	26		T268	13		T304	12
auto[0]	values[2]	values[4]	299	1			T24	91		T101	20		T73	10
auto[0]	values[2]	values[5]	207	1			T108	11		T72	7		T202	10
auto[0]	values[2]	values[6]	289	1			T305	18		T111	78		T256	13
auto[0]	values[2]	values[7]	278	1			T306	4		T111	35		T231	9
auto[0]	values[3]	values[0]	171	1			T246	12		T307	2		T170	10
auto[0]	values[3]	values[1]	209	1			T68	11		T72	19		T73	12
auto[0]	values[3]	values[2]	153	1			T168	11		T268	19		T308	10
auto[0]	values[3]	values[3]	307	1			T73	119		T230	12		T285	13
auto[0]	values[3]	values[4]	312	1			T52	8		T108	9		T233	20
auto[0]	values[3]	values[5]	159	1			T51	10		T289	15		T273	13
auto[0]	values[3]	values[6]	131	1			T231	9		T246	11		T250	9
auto[0]	values[3]	values[7]	173	1			T309	2		T235	15		T310	9
auto[0]	values[4]	values[0]	268	1			T15	14		T57	10		T235	10
auto[0]	values[4]	values[1]	445	1			T68	7		T72	5		T311	4
auto[0]	values[4]	values[2]	135	1			T204	18		T42	30		T229	12
auto[0]	values[4]	values[3]	283	1			T56	64		T52	16		T68	31
auto[0]	values[4]	values[4]	346	1			T58	14		T108	10		T312	2
auto[0]	values[4]	values[5]	117	1			T313	22		T231	22		T314	10
auto[0]	values[4]	values[6]	195	1			T71	11		T111	60		T285	11
auto[0]	values[4]	values[7]	230	1			T108	12		T206	8		T292	16
auto[0]	values[5]	values[0]	211	1			T108	10		T231	15		T286	9
auto[0]	values[5]	values[1]	374	1			T67	4		T51	11		T315	6
auto[0]	values[5]	values[2]	416	1			T68	187		T91	2		T265	6
auto[0]	values[5]	values[3]	456	1			T244	8		T285	8		T273	11
auto[0]	values[5]	values[4]	308	1			T63	18		T122	14		T316	51
auto[0]	values[5]	values[5]	233	1			T267	14		T246	27		T170	13
auto[0]	values[5]	values[6]	315	1			T17	24		T62	14		T82	64
auto[0]	values[5]	values[7]	289	1			T235	13		T170	29		T317	12
auto[0]	values[6]	values[0]	291	1			T68	15		T72	9		T318	16
auto[0]	values[6]	values[1]	325	1			T122	15		T111	11		T275	10
auto[0]	values[6]	values[2]	261	1			T119	136		T285	13		T319	8
auto[0]	values[6]	values[3]	261	1			T241	10		T277	8		T72	11
auto[0]	values[6]	values[4]	215	1			T59	10		T264	10		T235	15
auto[0]	values[6]	values[5]	157	1			T72	13		T73	22		T289	11
auto[0]	values[6]	values[6]	164	1			T97	4		T320	4		T231	11
auto[0]	values[6]	values[7]	508	1			T105	6		T73	8		T321	6
auto[0]	values[7]	values[0]	206	1			T72	15		T222	2		T256	14
auto[0]	values[7]	values[1]	361	1			T65	12		T72	12		T322	10
auto[0]	values[7]	values[2]	174	1			T22	6		T73	15		T323	12
auto[0]	values[7]	values[3]	251	1			T106	4		T72	10		T324	6
auto[0]	values[7]	values[4]	246	1			T325	4		T202	14		T235	12
auto[0]	values[7]	values[5]	161	1			T104	10		T168	25		T326	6
auto[0]	values[7]	values[6]	156	1			T65	12		T73	13		T233	8
auto[0]	values[7]	values[7]	213	1			T75	14		T51	13		T108	13
auto[1]	values[0]	values[0]	196	1			T111	57		T231	2		T246	9
auto[1]	values[0]	values[1]	351	1			T68	59		T69	14		T72	14
auto[1]	values[0]	values[2]	277	1			T68	8		T246	7		T170	10
auto[1]	values[0]	values[3]	231	1			T23	16		T51	24		T111	12
auto[1]	values[0]	values[4]	335	1			T72	121		T103	19		T122	9
auto[1]	values[0]	values[5]	81	1			T68	8		T71	9		T240	6
auto[1]	values[0]	values[6]	110	1			T122	15		T168	4		T327	11
auto[1]	values[0]	values[7]	138	1			T52	7		T68	3		T73	6
auto[1]	values[1]	values[0]	212	1			T51	9		T280	22		T289	6
auto[1]	values[1]	values[1]	174	1			T73	8		T202	6		T122	7
auto[1]	values[1]	values[2]	155	1			T111	9		T231	10		T328	8
auto[1]	values[1]	values[3]	247	1			T111	78		T329	12		T256	5
auto[1]	values[1]	values[4]	78	1			T68	13		T111	11		T266	6
auto[1]	values[1]	values[5]	153	1			T108	7		T68	9		T235	12
auto[1]	values[1]	values[6]	87	1			T68	5		T111	7		T263	20
auto[1]	values[1]	values[7]	129	1			T71	5		T72	11		T162	9
auto[1]	values[2]	values[0]	120	1			T225	12		T42	8		T194	12
auto[1]	values[2]	values[1]	189	1			T70	20		T284	14		T285	29
auto[1]	values[2]	values[2]	114	1			T72	6		T73	19		T330	8
auto[1]	values[2]	values[3]	79	1			T72	8		T268	7		T331	24
auto[1]	values[2]	values[4]	98	1			T73	19		T256	6		T228	12
auto[1]	values[2]	values[5]	283	1			T203	4		T108	9		T72	51
auto[1]	values[2]	values[6]	179	1			T111	14		T256	7		T194	21
auto[1]	values[2]	values[7]	163	1			T111	17		T231	15		T332	4
auto[1]	values[3]	values[0]	194	1			T246	44		T170	47		T333	7
auto[1]	values[3]	values[1]	219	1			T68	21		T72	9		T73	70
auto[1]	values[3]	values[2]	83	1			T334	12		T335	18		T168	9
auto[1]	values[3]	values[3]	107	1			T73	11		T74	16		T285	13
auto[1]	values[3]	values[4]	171	1			T52	12		T108	11		T233	26
auto[1]	values[3]	values[5]	109	1			T51	25		T289	5		T273	7
auto[1]	values[3]	values[6]	178	1			T231	11		T246	10		T336	20
auto[1]	values[3]	values[7]	126	1			T235	9		T310	14		T337	44
auto[1]	values[4]	values[0]	154	1			T61	6		T235	10		T285	25
auto[1]	values[4]	values[1]	241	1			T68	51		T72	15		T170	8
auto[1]	values[4]	values[2]	84	1			T42	23		T229	9		T326	6
auto[1]	values[4]	values[3]	119	1			T52	4		T68	8		T286	13
auto[1]	values[4]	values[4]	95	1			T108	10		T231	8		T272	7
auto[1]	values[4]	values[5]	103	1			T64	16		T231	11		T269	6
auto[1]	values[4]	values[6]	144	1			T71	9		T111	7		T285	16
auto[1]	values[4]	values[7]	100	1			T108	8		T338	6		T170	10
auto[1]	values[5]	values[0]	169	1			T108	10		T231	5		T286	22
auto[1]	values[5]	values[1]	154	1			T51	9		T285	9		T253	11
auto[1]	values[5]	values[2]	162	1			T68	7		T122	4		T231	8
auto[1]	values[5]	values[3]	253	1			T285	12		T273	10		T256	10
auto[1]	values[5]	values[4]	200	1			T122	6		T231	22		T240	12
auto[1]	values[5]	values[5]	257	1			T246	47		T170	7		T257	7
auto[1]	values[5]	values[6]	150	1			T52	6		T246	8		T272	12
auto[1]	values[5]	values[7]	186	1			T235	10		T170	5		T317	8
auto[1]	values[6]	values[0]	105	1			T16	4		T68	9		T72	11
auto[1]	values[6]	values[1]	161	1			T122	5		T111	51		T168	10
auto[1]	values[6]	values[2]	140	1			T285	26		T339	66		T115	11
auto[1]	values[6]	values[3]	218	1			T72	26		T111	43		T337	4
auto[1]	values[6]	values[4]	79	1			T235	5		T240	12		T233	6
auto[1]	values[6]	values[5]	81	1			T72	7		T73	8		T289	11
auto[1]	values[6]	values[6]	128	1			T231	14		T256	57		T257	11
auto[1]	values[6]	values[7]	248	1			T73	12		T122	10		T340	9
auto[1]	values[7]	values[0]	267	1			T66	14		T72	5		T256	6
auto[1]	values[7]	values[1]	281	1			T65	8		T72	8		T246	63
auto[1]	values[7]	values[2]	124	1			T73	5		T341	13		T276	22
auto[1]	values[7]	values[3]	134	1			T72	10		T240	11		T342	10
auto[1]	values[7]	values[4]	168	1			T202	14		T235	8		T240	7
auto[1]	values[7]	values[5]	138	1			T168	10		T326	19		T268	6
auto[1]	values[7]	values[6]	212	1			T65	112		T73	7		T233	13
auto[1]	values[7]	values[7]	215	1			T51	7		T108	7		T73	8