Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	317	1			T104	2		T51	4		T78	4
auto[ReadAddrCrossIntoMailbox]	265	1			T51	2		T52	2		T68	7
auto[ReadAddrCrossOutOfMailbox]	262	1			T51	2		T52	5		T68	10
auto[ReadAddrCrossAllMailbox]	193	1			T51	3		T52	1		T68	3
auto[ReadAddrOutsideMailbox]	3059	1			T15	2		T16	2		T17	6

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2035

1

T15

1

T16

1

T17

3

auto[1]

2061

1

T15

1

T16

1

T17

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	692	1			T16	2		T21	2		T24	2
read_ops[0x0b]	736	1			T17	2		T56	2		T64	2
read_ops[0x3b]	661	1			T57	4		T82	6		T51	2
read_ops[0x6b]	660	1			T15	2		T57	2		T203	2
read_ops[0xbb]	667	1			T17	2		T59	4		T65	2
read_ops[0xeb]	680	1			T17	2		T104	2		T65	1

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	29	1			T78	2		T206	1		T94	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T78	2		T206	1		T94	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	33	1			T68	1		T73	1		T202	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	10	1			T271	1		T231	1		T343	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	32	1			T68	1		T264	1		T122	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	17	1			T52	1		T264	1		T286	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	22	1			T52	1		T235	1		T231	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T51	1		T285	1		T168	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	263	1			T16	1		T21	1		T24	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	241	1			T16	1		T21	1		T24	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	25	1			T68	2		T94	1		T271	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	30	1			T51	1		T68	1		T94	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T68	1		T72	1		T273	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T73	1		T235	1		T231	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T52	1		T68	3		T271	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T68	1		T72	1		T73	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T51	1		T68	1		T302	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	12	1			T72	1		T302	1		T122	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	257	1			T17	1		T56	1		T64	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	291	1			T17	1		T56	1		T64	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	27	1			T94	1		T72	1		T264	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	28	1			T94	1		T264	1		T302	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	18	1			T51	1		T264	1		T302	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	13	1			T52	1		T68	1		T264	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	18	1			T51	1		T72	1		T240	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T52	1		T72	1		T111	2
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	12	1			T72	1		T73	1		T246	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	12	1			T122	1		T231	1		T257	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	254	1			T57	2		T82	3		T108	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	255	1			T57	2		T82	3		T108	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	25	1			T111	2		T240	1		T344	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	20	1			T52	1		T68	1		T231	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T52	1		T302	1		T285	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T68	1		T73	1		T302	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	24	1			T73	1		T271	1		T231	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	20	1			T52	1		T271	1		T122	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T240	1		T323	2		T256	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T51	1		T73	1		T231	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	243	1			T15	1		T57	1		T203	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	253	1			T15	1		T57	1		T203	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T51	1		T206	1		T240	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T51	1		T206	1		T68	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	31	1			T68	2		T73	2		T309	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T68	1		T72	1		T73	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	15	1			T68	1		T72	1		T122	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T52	1		T68	1		T73	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T240	1		T344	1		T317	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T122	1		T235	1		T286	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	223	1			T17	1		T59	2		T75	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	249	1			T17	1		T59	2		T65	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T104	1		T51	1		T68	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	19	1			T104	1		T68	1		T231	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	17	1			T231	1		T285	1		T162	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T51	1		T103	1		T231	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	20	1			T51	1		T68	2		T72	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	18	1			T68	1		T73	1		T231	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T231	2		T240	1		T285	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	12	1			T68	2		T231	1		T168	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	253	1			T17	1		T61	1		T51	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	277	1			T17	1		T65	1		T61	1