Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3975	1			T16	4		T56	64		T78	8
values[1]	3381	1			T22	6		T57	10		T64	16
values[2]	2787	1			T66	14		T65	124		T203	4
values[3]	3079	1			T23	16		T62	14		T82	64
values[4]	3305	1			T21	2		T223	6		T68	159
values[5]	3679	1			T15	14		T17	24		T101	20
values[6]	3514	1			T24	91		T104	10		T105	6
values[7]	3520	1			T241	10		T108	20		T68	57

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3428	1			T66	14		T106	4		T51	40
values[1]	3511	1			T17	24		T58	14		T59	10
values[2]	3150	1			T23	16		T65	20		T75	14
values[3]	3782	1			T63	18		T82	64		T61	6
values[4]	3304	1			T16	4		T21	2		T105	6
values[5]	3506	1			T15	14		T24	91		T57	10
values[6]	2905	1			T22	6		T56	64		T101	20
values[7]	3654	1			T64	16		T104	10		T241	10

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26603

1

T15

14

T16

4

T17

24

auto[1]

637

1

T65

1

T61

2

T51

4

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	292	1			T72	20		T111	38		T316	51
auto[0]	values[0]	values[1]	478	1			T318	16		T230	12		T234	24
auto[0]	values[0]	values[2]	528	1			T243	24		T68	31		T202	27
auto[0]	values[0]	values[3]	471	1			T68	193		T72	20		T264	10
auto[0]	values[0]	values[4]	698	1			T16	4		T78	8		T68	123
auto[0]	values[0]	values[5]	519	1			T108	20		T252	6		T233	20
auto[0]	values[0]	values[6]	443	1			T56	64		T325	4		T73	45
auto[0]	values[0]	values[7]	456	1			T206	8		T240	20		T228	23
auto[0]	values[1]	values[0]	362	1			T285	38		T345	18		T346	24
auto[0]	values[1]	values[1]	601	1			T60	24		T52	20		T71	19
auto[0]	values[1]	values[2]	405	1			T108	19		T72	71		T168	20
auto[0]	values[1]	values[3]	568	1			T73	29		T285	39		T170	207
auto[0]	values[1]	values[4]	202	1			T72	33		T307	2		T273	21
auto[0]	values[1]	values[5]	486	1			T57	10		T111	57		T231	19
auto[0]	values[1]	values[6]	349	1			T22	6		T272	20		T275	10
auto[0]	values[1]	values[7]	325	1			T64	16		T68	23		T338	6
auto[0]	values[2]	values[0]	319	1			T66	14		T265	6		T222	2
auto[0]	values[2]	values[1]	174	1			T335	14		T256	22		T314	10
auto[0]	values[2]	values[2]	310	1			T71	19		T232	20		T162	22
auto[0]	values[2]	values[3]	232	1			T306	4		T204	18		T296	8
auto[0]	values[2]	values[4]	358	1			T305	18		T73	17		T229	50
auto[0]	values[2]	values[5]	597	1			T65	123		T203	4		T77	2
auto[0]	values[2]	values[6]	382	1			T71	20		T235	20		T347	6
auto[0]	values[2]	values[7]	344	1			T122	20		T231	28		T253	35
auto[0]	values[3]	values[0]	396	1			T51	20		T72	20		T289	21
auto[0]	values[3]	values[1]	464	1			T348	4		T349	14		T310	22
auto[0]	values[3]	values[2]	237	1			T23	16		T73	20		T235	23
auto[0]	values[3]	values[3]	603	1			T82	64		T122	20		T350	46
auto[0]	values[3]	values[4]	249	1			T73	59		T351	6		T240	18
auto[0]	values[3]	values[5]	268	1			T62	14		T111	20		T284	14
auto[0]	values[3]	values[6]	253	1			T51	34		T73	20		T235	20
auto[0]	values[3]	values[7]	542	1			T68	154		T267	14		T72	19
auto[0]	values[4]	values[0]	570	1			T73	82		T321	6		T315	6
auto[0]	values[4]	values[1]	499	1			T223	6		T68	32		T245	20
auto[0]	values[4]	values[2]	321	1			T97	4		T72	130		T286	28
auto[0]	values[4]	values[3]	337	1			T285	22		T246	27		T319	8
auto[0]	values[4]	values[4]	496	1			T21	2		T72	18		T111	86
auto[0]	values[4]	values[5]	242	1			T74	14		T352	2		T285	32
auto[0]	values[4]	values[6]	268	1			T302	8		T103	21		T122	20
auto[0]	values[4]	values[7]	485	1			T68	127		T231	20		T332	4
auto[0]	values[5]	values[0]	455	1			T51	20		T108	20		T69	12
auto[0]	values[5]	values[1]	589	1			T17	24		T52	20		T73	20
auto[0]	values[5]	values[2]	417	1			T111	91		T256	20		T257	18
auto[0]	values[5]	values[3]	527	1			T63	18		T119	136		T122	20
auto[0]	values[5]	values[4]	291	1			T108	20		T292	16		T162	20
auto[0]	values[5]	values[5]	367	1			T15	14		T67	4		T70	14
auto[0]	values[5]	values[6]	525	1			T101	20		T91	2		T313	22
auto[0]	values[5]	values[7]	418	1			T72	20		T111	102		T240	19
auto[0]	values[6]	values[0]	294	1			T106	4		T72	37		T342	8
auto[0]	values[6]	values[1]	383	1			T58	14		T59	10		T51	30
auto[0]	values[6]	values[2]	515	1			T65	20		T75	14		T235	18
auto[0]	values[6]	values[3]	402	1			T61	4		T277	8		T111	20
auto[0]	values[6]	values[4]	453	1			T105	6		T52	19		T244	8
auto[0]	values[6]	values[5]	560	1			T24	91		T343	2		T353	2
auto[0]	values[6]	values[6]	443	1			T297	2		T111	66		T235	22
auto[0]	values[6]	values[7]	383	1			T104	10		T51	50		T108	20
auto[0]	values[7]	values[0]	668	1			T108	20		T334	12		T202	22
auto[0]	values[7]	values[1]	248	1			T72	29		T257	20		T263	37
auto[0]	values[7]	values[2]	315	1			T68	57		T280	18		T240	19
auto[0]	values[7]	values[3]	570	1			T240	20		T233	26		T299	16
auto[0]	values[7]	values[4]	468	1			T72	20		T73	28		T122	20
auto[0]	values[7]	values[5]	373	1			T202	20		T231	52		T354	6
auto[0]	values[7]	values[6]	186	1			T300	18		T225	20		T355	6
auto[0]	values[7]	values[7]	624	1			T241	10		T238	6		T246	21
auto[1]	values[0]	values[0]	7	1			T111	1		T327	1		T356	3
auto[1]	values[0]	values[1]	9	1			T285	1		T170	1		T228	2
auto[1]	values[0]	values[2]	9	1			T68	1		T202	1		T272	1
auto[1]	values[0]	values[3]	7	1			T68	1		T111	1		T228	2
auto[1]	values[0]	values[4]	14	1			T68	1		T111	1		T225	1
auto[1]	values[0]	values[5]	21	1			T233	3		T246	1		T194	1
auto[1]	values[0]	values[6]	9	1			T256	1		T172	2		T357	3
auto[1]	values[0]	values[7]	14	1			T358	6		T86	1		T359	2
auto[1]	values[1]	values[0]	11	1			T285	1		T276	1		T360	1
auto[1]	values[1]	values[1]	8	1			T71	1		T231	1		T246	2
auto[1]	values[1]	values[2]	7	1			T108	1		T72	3		T333	1
auto[1]	values[1]	values[3]	25	1			T73	1		T285	7		T170	6
auto[1]	values[1]	values[4]	5	1			T72	1		T88	1		T361	3
auto[1]	values[1]	values[5]	15	1			T111	1		T231	4		T276	1
auto[1]	values[1]	values[6]	5	1			T362	1		T363	1		T115	1
auto[1]	values[1]	values[7]	7	1			T68	1		T273	2		T88	1
auto[1]	values[2]	values[0]	8	1			T122	3		T266	2		T364	1
auto[1]	values[2]	values[1]	6	1			T335	4		T365	1		T85	1
auto[1]	values[2]	values[2]	15	1			T71	1		T162	1		T168	1
auto[1]	values[2]	values[3]	3	1			T366	1		T367	2		-	-
auto[1]	values[2]	values[4]	14	1			T73	3		T229	1		T368	2
auto[1]	values[2]	values[5]	9	1			T65	1		T52	2		T337	2
auto[1]	values[2]	values[6]	10	1			T263	1		T326	1		T268	1
auto[1]	values[2]	values[7]	6	1			T231	2		T253	1		T365	3
auto[1]	values[3]	values[0]	8	1			T289	1		T231	2		T337	2
auto[1]	values[3]	values[1]	8	1			T310	1		T369	2		T370	2
auto[1]	values[3]	values[2]	9	1			T235	1		T256	1		T194	1
auto[1]	values[3]	values[3]	8	1			T276	1		T328	1		T172	1
auto[1]	values[3]	values[4]	10	1			T240	2		T256	2		T371	2
auto[1]	values[3]	values[5]	9	1			T370	2		T357	2		T372	2
auto[1]	values[3]	values[6]	3	1			T51	1		T194	1		T357	1
auto[1]	values[3]	values[7]	12	1			T68	3		T72	1		T253	2
auto[1]	values[4]	values[0]	15	1			T231	1		T162	3		T326	1
auto[1]	values[4]	values[1]	11	1			T285	4		T286	1		T373	2
auto[1]	values[4]	values[2]	13	1			T72	1		T286	3		T256	2
auto[1]	values[4]	values[3]	10	1			T285	4		T246	1		T326	1
auto[1]	values[4]	values[4]	12	1			T72	2		T111	1		T268	3
auto[1]	values[4]	values[5]	6	1			T74	2		T285	1		T89	3
auto[1]	values[4]	values[6]	8	1			T103	2		T285	1		T250	2
auto[1]	values[4]	values[7]	12	1			T253	2		T86	2		T115	3
auto[1]	values[5]	values[0]	6	1			T69	2		T73	2		T86	1
auto[1]	values[5]	values[1]	19	1			T246	1		T256	1		T276	3
auto[1]	values[5]	values[2]	15	1			T111	1		T257	2		T326	1
auto[1]	values[5]	values[3]	3	1			T365	1		T85	2		-	-
auto[1]	values[5]	values[4]	2	1			T269	2		-	-		-	-
auto[1]	values[5]	values[5]	20	1			T70	6		T225	1		T374	2
auto[1]	values[5]	values[6]	11	1			T231	1		T256	3		T42	5
auto[1]	values[5]	values[7]	14	1			T111	3		T240	1		T328	1
auto[1]	values[6]	values[0]	4	1			T342	2		T375	1		T361	1
auto[1]	values[6]	values[1]	9	1			T51	3		T108	1		T72	1
auto[1]	values[6]	values[2]	17	1			T235	2		T229	2		T364	2
auto[1]	values[6]	values[3]	6	1			T61	2		T365	1		T376	3
auto[1]	values[6]	values[4]	23	1			T52	1		T233	1		T257	2
auto[1]	values[6]	values[5]	8	1			T377	4		T378	2		T379	1
auto[1]	values[6]	values[6]	6	1			T111	1		T235	1		T337	1
auto[1]	values[6]	values[7]	8	1			T72	2		T285	6		-	-
auto[1]	values[7]	values[0]	13	1			T246	3		T170	1		T85	3
auto[1]	values[7]	values[1]	5	1			T263	3		T326	1		T380	1
auto[1]	values[7]	values[2]	17	1			T280	4		T240	1		T381	6
auto[1]	values[7]	values[3]	10	1			T228	1		T225	1		T268	1
auto[1]	values[7]	values[4]	9	1			T73	2		T382	1		T383	1
auto[1]	values[7]	values[5]	6	1			T231	1		T384	2		T361	3
auto[1]	values[7]	values[6]	4	1			T355	2		T379	1		T385	1
auto[1]	values[7]	values[7]	4	1			T276	1		T383	2		T376	1