Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	841	1			T33	17		T34	14		T36	31
all_values[1]	841	1			T33	17		T34	14		T36	31
all_values[2]	841	1			T33	17		T34	14		T36	31
all_values[3]	841	1			T33	17		T34	14		T36	31
all_values[4]	841	1			T33	17		T34	14		T36	31
all_values[5]	841	1			T33	17		T34	14		T36	31
all_values[6]	841	1			T33	17		T34	14		T36	31
all_values[7]	841	1			T33	17		T34	14		T36	31

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3665

1

T33

67

T34

58

T36

136

auto[1]

3063

1

T33

69

T34

54

T36

112

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2670

1

T33

53

T34

30

T36

92

auto[1]

4058

1

T33

83

T34

82

T36

156

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3844

1

T33

71

T34

58

T36

132

auto[1]

2884

1

T33

65

T34

54

T36

116

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	181	1			T33	5		T34	1		T36	5
all_values[0]	auto[0]	auto[0]	auto[1]	90	1			T33	2		T34	4		T36	3
all_values[0]	auto[0]	auto[1]	auto[0]	145	1			T33	3		T34	2		T36	6
all_values[0]	auto[0]	auto[1]	auto[1]	75	1			T33	2		T34	2		T36	2
all_values[0]	auto[1]	auto[0]	auto[1]	208	1			T33	5		T34	1		T36	9
all_values[0]	auto[1]	auto[1]	auto[1]	142	1			T34	4		T36	6		T37	3
all_values[1]	auto[0]	auto[0]	auto[0]	174	1			T34	1		T36	5		T37	7
all_values[1]	auto[0]	auto[0]	auto[1]	77	1			T33	3		T34	5		T36	3
all_values[1]	auto[0]	auto[1]	auto[0]	141	1			T33	1		T34	1		T36	6
all_values[1]	auto[0]	auto[1]	auto[1]	74	1			T33	1		T36	3		T38	4
all_values[1]	auto[1]	auto[0]	auto[1]	210	1			T33	5		T34	5		T36	11
all_values[1]	auto[1]	auto[1]	auto[1]	165	1			T33	7		T34	2		T36	3
all_values[2]	auto[0]	auto[0]	auto[0]	155	1			T33	3		T34	1		T36	2
all_values[2]	auto[0]	auto[0]	auto[1]	98	1			T34	1		T36	7		T38	10
all_values[2]	auto[0]	auto[1]	auto[0]	131	1			T33	3		T34	3		T36	2
all_values[2]	auto[0]	auto[1]	auto[1]	88	1			T33	2		T34	2		T36	3
all_values[2]	auto[1]	auto[0]	auto[1]	207	1			T33	5		T34	3		T36	5
all_values[2]	auto[1]	auto[1]	auto[1]	162	1			T33	4		T34	4		T36	12
all_values[3]	auto[0]	auto[0]	auto[0]	161	1			T33	5		T34	2		T36	9
all_values[3]	auto[0]	auto[0]	auto[1]	87	1			T36	1		T38	3		T190	2
all_values[3]	auto[0]	auto[1]	auto[0]	148	1			T33	2		T36	7		T38	5
all_values[3]	auto[0]	auto[1]	auto[1]	83	1			T33	1		T34	3		T36	2
all_values[3]	auto[1]	auto[0]	auto[1]	202	1			T33	4		T34	2		T36	8
all_values[3]	auto[1]	auto[1]	auto[1]	160	1			T33	5		T34	7		T36	4
all_values[4]	auto[0]	auto[0]	auto[0]	197	1			T33	3		T34	2		T36	11
all_values[4]	auto[0]	auto[0]	auto[1]	92	1			T33	1		T34	3		T36	4
all_values[4]	auto[0]	auto[1]	auto[0]	142	1			T33	8		T34	1		T36	3
all_values[4]	auto[0]	auto[1]	auto[1]	80	1			T36	1		T37	1		T38	1
all_values[4]	auto[1]	auto[0]	auto[1]	184	1			T33	4		T34	6		T36	7
all_values[4]	auto[1]	auto[1]	auto[1]	146	1			T33	1		T34	2		T36	5
all_values[5]	auto[0]	auto[0]	auto[0]	238	1			T33	4		T34	5		T36	8
all_values[5]	auto[0]	auto[1]	auto[0]	236	1			T33	4		T34	5		T36	7
all_values[5]	auto[1]	auto[0]	auto[1]	194	1			T33	3		T34	4		T36	8
all_values[5]	auto[1]	auto[1]	auto[1]	173	1			T33	6		T36	8		T37	2
all_values[6]	auto[0]	auto[0]	auto[0]	185	1			T33	5		T34	3		T36	6
all_values[6]	auto[0]	auto[0]	auto[1]	83	1			T34	2		T36	3		T37	3
all_values[6]	auto[0]	auto[1]	auto[0]	135	1			T33	2		T34	1		T36	6
all_values[6]	auto[0]	auto[1]	auto[1]	92	1			T33	2		T34	2		T36	3
all_values[6]	auto[1]	auto[0]	auto[1]	171	1			T33	5		T34	1		T36	6
all_values[6]	auto[1]	auto[1]	auto[1]	175	1			T33	3		T34	5		T36	7
all_values[7]	auto[0]	auto[0]	auto[0]	165	1			T33	1		T36	4		T37	3
all_values[7]	auto[0]	auto[0]	auto[1]	70	1			T33	1		T34	3		T38	8
all_values[7]	auto[0]	auto[1]	auto[0]	136	1			T33	4		T34	2		T36	5
all_values[7]	auto[0]	auto[1]	auto[1]	85	1			T33	3		T34	1		T36	5
all_values[7]	auto[1]	auto[0]	auto[1]	236	1			T33	3		T34	3		T36	11
all_values[7]	auto[1]	auto[1]	auto[1]	149	1			T33	5		T34	5		T36	6

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal