Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1833

1

T5

1

T10

4

T27

4

auto[1]

1898

1

T5

1

T6

1

T10

5

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1972

1

T6

1

T31

1

T48

2

auto[1]

1759

1

T5

2

T10

9

T27

5

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2978

1

T5

2

T10

9

T27

5

auto[1]

753

1

T6

1

T31

1

T45

4

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	743	1			T10	2		T29	9		T30	5
valid[1]	760	1			T10	1		T27	1		T29	4
valid[2]	758	1			T5	1		T10	1		T29	7
valid[3]	752	1			T6	1		T10	3		T27	2
valid[4]	718	1			T5	1		T10	2		T27	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	131	1			T45	1		T37	3		T391	1
auto[0]	auto[0]	valid[0]	auto[1]	178	1			T10	1		T29	4		T30	2
auto[0]	auto[0]	valid[1]	auto[0]	117	1			T81	4		T34	1		T51	1
auto[0]	auto[0]	valid[1]	auto[1]	169	1			T10	1		T27	1		T29	3
auto[0]	auto[0]	valid[2]	auto[0]	118	1			T80	1		T81	1		T34	3
auto[0]	auto[0]	valid[2]	auto[1]	177	1			T10	1		T29	4		T30	3
auto[0]	auto[0]	valid[3]	auto[0]	117	1			T48	1		T45	1		T80	1
auto[0]	auto[0]	valid[3]	auto[1]	163	1			T10	1		T27	1		T29	2
auto[0]	auto[0]	valid[4]	auto[0]	117	1			T48	1		T45	2		T80	2
auto[0]	auto[0]	valid[4]	auto[1]	172	1			T5	1		T27	2		T29	6
auto[0]	auto[1]	valid[0]	auto[0]	114	1			T80	2		T391	1		T397	1
auto[0]	auto[1]	valid[0]	auto[1]	174	1			T10	1		T29	5		T30	3
auto[0]	auto[1]	valid[1]	auto[0]	129	1			T81	1		T34	3		T51	2
auto[0]	auto[1]	valid[1]	auto[1]	183	1			T29	1		T30	2		T117	1
auto[0]	auto[1]	valid[2]	auto[0]	117	1			T45	1		T46	2		T80	2
auto[0]	auto[1]	valid[2]	auto[1]	186	1			T5	1		T29	3		T30	1
auto[0]	auto[1]	valid[3]	auto[0]	141	1			T45	2		T80	2		T81	1
auto[0]	auto[1]	valid[3]	auto[1]	193	1			T10	2		T27	1		T29	8
auto[0]	auto[1]	valid[4]	auto[0]	118	1			T45	1		T46	1		T80	1
auto[0]	auto[1]	valid[4]	auto[1]	164	1			T10	2		T29	3		T30	3
auto[1]	auto[0]	valid[0]	auto[0]	69	1			T45	1		T80	1		T81	1
auto[1]	auto[0]	valid[1]	auto[0]	90	1			T31	1		T45	1		T81	2
auto[1]	auto[0]	valid[2]	auto[0]	72	1			T81	1		T34	1		T391	1
auto[1]	auto[0]	valid[3]	auto[0]	74	1			T46	1		T81	2		T51	1
auto[1]	auto[0]	valid[4]	auto[0]	69	1			T34	2		T37	1		T259	1
auto[1]	auto[1]	valid[0]	auto[0]	77	1			T81	1		T34	1		T397	1
auto[1]	auto[1]	valid[1]	auto[0]	72	1			T80	1		T391	1		T397	1
auto[1]	auto[1]	valid[2]	auto[0]	88	1			T45	1		T80	3		T53	1
auto[1]	auto[1]	valid[3]	auto[0]	64	1			T6	1		T51	1		T53	1
auto[1]	auto[1]	valid[4]	auto[0]	78	1			T45	1		T46	1		T81	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal