Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50712

1

T6

38

T7

6

T11

4

auto[1]

18457

1

T5

2

T6

14

T10

9

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50799

1

T5

2

T6

33

T7

6

auto[1]

18370

1

T6

19

T11

2

T28

4

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	35478	1			T5	2		T6	31		T7	6
others[1]	5863	1			T6	4		T28	1		T29	42
others[2]	5854	1			T6	6		T11	1		T29	27
others[3]	6613	1			T6	6		T28	2		T29	39
interest[1]	3910	1			T6	1		T28	3		T29	24
interest[4]	23246	1			T5	2		T6	19		T7	2
interest[64]	11451	1			T6	4		T11	1		T28	5

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	16542	1			T6	12		T7	6		T11	1
auto[0]	auto[0]	others[1]	2714	1			T6	2		T28	1		T45	10
auto[0]	auto[0]	others[2]	2738	1			T6	3		T11	1		T45	20
auto[0]	auto[0]	others[3]	3138	1			T28	1		T45	10		T46	8
auto[0]	auto[0]	interest[1]	1831	1			T6	1		T28	3		T45	17
auto[0]	auto[0]	interest[4]	10778	1			T6	7		T7	2		T48	3
auto[0]	auto[0]	interest[64]	5379	1			T6	1		T28	3		T31	1
auto[0]	auto[1]	others[0]	9622	1			T5	2		T6	8		T10	9
auto[0]	auto[1]	others[1]	1539	1			T6	1		T29	42		T30	40
auto[0]	auto[1]	others[2]	1545	1			T6	1		T29	27		T30	35
auto[0]	auto[1]	others[3]	1683	1			T6	2		T29	39		T30	33
auto[0]	auto[1]	interest[1]	1054	1			T29	24		T30	21		T45	1
auto[0]	auto[1]	interest[4]	6379	1			T5	2		T6	5		T10	9
auto[0]	auto[1]	interest[64]	3014	1			T6	2		T29	65		T30	54
auto[1]	auto[0]	others[0]	9314	1			T6	11		T11	1		T28	1
auto[1]	auto[0]	others[1]	1610	1			T6	1		T45	11		T46	7
auto[1]	auto[0]	others[2]	1571	1			T6	2		T31	2		T45	10
auto[1]	auto[0]	others[3]	1792	1			T6	4		T28	1		T31	2
auto[1]	auto[0]	interest[1]	1025	1			T48	1		T45	3		T46	3
auto[1]	auto[0]	interest[4]	6089	1			T6	7		T11	1		T28	1
auto[1]	auto[0]	interest[64]	3058	1			T6	1		T11	1		T28	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal