Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2421079	1			T1	1		T3	1		T4	22
all_values[1]	2421079	1			T1	1		T3	1		T4	22
all_values[2]	2421079	1			T1	1		T3	1		T4	22
all_values[3]	2421079	1			T1	1		T3	1		T4	22
all_values[4]	2421079	1			T1	1		T3	1		T4	22
all_values[5]	2421079	1			T1	1		T3	1		T4	22
all_values[6]	2421079	1			T1	1		T3	1		T4	22
all_values[7]	2421079	1			T1	1		T3	1		T4	22

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18849730

1

T1

8

T3

8

T4

176

auto[1]

518902

1

T33

116

T35

37

T36

162

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19341327

1

T1

8

T3

8

T4

176

auto[1]

27305

1

T32

126

T33

105

T49

14

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2344978	1			T1	1		T3	1		T4	22
all_values[0]	auto[0]	auto[1]	12496	1			T32	63		T33	7		T49	11
all_values[0]	auto[1]	auto[0]	62700	1			T33	5		T35	4		T36	10
all_values[0]	auto[1]	auto[1]	905	1			T33	8		T36	8		T37	2
all_values[1]	auto[0]	auto[0]	2331988	1			T1	1		T3	1		T4	22
all_values[1]	auto[0]	auto[1]	7566	1			T32	63		T33	4		T49	2
all_values[1]	auto[1]	auto[0]	80725	1			T33	6		T35	1		T36	12
all_values[1]	auto[1]	auto[1]	800	1			T33	5		T35	4		T36	7
all_values[2]	auto[0]	auto[0]	2341760	1			T1	1		T3	1		T4	22
all_values[2]	auto[0]	auto[1]	2884	1			T33	6		T49	1		T35	4
all_values[2]	auto[1]	auto[0]	76046	1			T33	9		T35	3		T36	14
all_values[2]	auto[1]	auto[1]	389	1			T33	8		T35	2		T36	5
all_values[3]	auto[0]	auto[0]	2327320	1			T1	1		T3	1		T4	22
all_values[3]	auto[0]	auto[1]	258	1			T33	8		T35	1		T36	7
all_values[3]	auto[1]	auto[0]	93256	1			T33	11		T35	7		T36	9
all_values[3]	auto[1]	auto[1]	245	1			T33	5		T36	14		T37	5
all_values[4]	auto[0]	auto[0]	2358857	1			T1	1		T3	1		T4	22
all_values[4]	auto[0]	auto[1]	222	1			T33	9		T35	1		T36	2
all_values[4]	auto[1]	auto[0]	61782	1			T33	6		T35	1		T36	14
all_values[4]	auto[1]	auto[1]	218	1			T33	8		T36	8		T37	5
all_values[5]	auto[0]	auto[0]	2362155	1			T1	1		T3	1		T4	22
all_values[5]	auto[0]	auto[1]	225	1			T33	10		T35	3		T36	7
all_values[5]	auto[1]	auto[0]	58492	1			T33	7		T35	4		T36	10
all_values[5]	auto[1]	auto[1]	207	1			T33	4		T35	4		T36	7
all_values[6]	auto[0]	auto[0]	2392668	1			T1	1		T3	1		T4	22
all_values[6]	auto[0]	auto[1]	227	1			T33	3		T35	5		T36	9
all_values[6]	auto[1]	auto[0]	27953	1			T33	18		T35	1		T36	13
all_values[6]	auto[1]	auto[1]	231	1			T33	5		T35	3		T36	7
all_values[7]	auto[0]	auto[0]	2365920	1			T1	1		T3	1		T4	22
all_values[7]	auto[0]	auto[1]	206	1			T33	9		T35	3		T36	3
all_values[7]	auto[1]	auto[0]	54727	1			T33	5		T35	2		T36	17
all_values[7]	auto[1]	auto[1]	226	1			T33	6		T35	1		T36	7