Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.08 98.44 94.08 98.62 89.36 97.27 95.56 99.26


Total tests in report: 1150
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
62.55 62.55 92.65 92.65 79.01 79.01 64.96 64.96 26.67 26.67 89.31 89.31 72.36 72.36 12.87 12.87 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/0.spi_device_intercept.4250371315
78.36 15.81 97.20 4.55 88.84 9.83 67.62 2.66 82.22 55.56 95.31 5.99 84.58 12.22 32.72 19.85 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_and_tpm_min_idle.3164024906
81.86 3.50 97.32 0.12 89.10 0.26 67.62 0.00 91.11 8.89 95.51 0.20 84.58 0.00 47.77 15.05 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_and_tpm.673026461
85.33 3.47 97.55 0.23 90.62 1.52 88.09 20.47 91.11 0.00 96.02 0.51 85.14 0.56 48.81 1.04 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_mode.4189610346
87.85 2.52 97.94 0.39 91.61 0.99 89.67 1.57 91.11 0.00 96.44 0.42 85.14 0.00 63.07 14.26 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/3.spi_device_stress_all.2562165640
89.40 1.54 97.94 0.00 91.74 0.12 90.06 0.39 91.11 0.00 96.48 0.03 93.61 8.47 64.85 1.78 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.305921646
90.30 0.91 97.94 0.00 91.74 0.00 90.06 0.00 91.11 0.00 96.48 0.00 93.61 0.00 71.19 6.34 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm.2120572700
91.17 0.86 98.19 0.25 92.57 0.83 90.45 0.39 93.33 2.22 96.87 0.39 94.03 0.42 72.72 1.53 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_all.3407885309
91.90 0.73 98.22 0.03 92.64 0.07 91.14 0.69 93.33 0.00 96.88 0.02 94.17 0.14 76.88 4.16 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/0.spi_device_stress_all.3853631033
92.57 0.68 98.23 0.01 92.64 0.00 95.87 4.72 93.33 0.00 96.88 0.00 94.17 0.00 76.88 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/0.spi_device_ram_cfg.3783386345
93.04 0.47 98.23 0.00 92.64 0.00 95.87 0.00 93.33 0.00 96.88 0.00 94.17 0.00 80.15 3.27 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.2109679918
93.43 0.39 98.23 0.00 92.64 0.00 95.87 0.00 93.33 0.00 96.88 0.00 94.17 0.00 82.87 2.72 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/8.spi_device_stress_all.224122599
93.80 0.37 98.24 0.01 92.68 0.04 98.03 2.17 93.33 0.00 96.90 0.02 94.31 0.14 83.12 0.25 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/0.spi_device_sec_cm.223323940
94.12 0.32 98.30 0.06 92.74 0.06 98.03 0.00 93.33 0.00 97.02 0.12 94.31 0.00 85.10 1.98 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_all.1691969473
94.40 0.28 98.32 0.03 92.78 0.04 98.03 0.00 93.33 0.00 97.09 0.07 94.31 0.00 86.93 1.83 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_and_tpm_min_idle.2139963397
94.63 0.23 98.32 0.00 92.78 0.00 98.03 0.00 93.33 0.00 97.09 0.00 94.31 0.00 88.51 1.58 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_and_tpm.2031466120
94.81 0.18 98.33 0.01 92.89 0.11 98.03 0.00 93.33 0.00 97.10 0.02 94.31 0.00 89.65 1.14 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.3980423784
94.98 0.18 98.33 0.00 92.89 0.00 98.03 0.00 93.33 0.00 97.10 0.00 94.31 0.00 90.89 1.24 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_and_tpm_min_idle.771522726
95.16 0.18 98.33 0.00 92.89 0.00 98.03 0.00 93.33 0.00 97.10 0.00 94.31 0.00 92.13 1.24 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_all.1417687835
95.30 0.14 98.33 0.00 92.89 0.00 98.03 0.00 93.33 0.00 97.10 0.00 95.28 0.97 92.13 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.536008996
95.43 0.13 98.34 0.01 92.90 0.01 98.03 0.00 93.33 0.00 97.10 0.00 95.28 0.00 93.02 0.89 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_mode_ignore_cmds.1186895989
95.55 0.12 98.34 0.00 92.90 0.00 98.03 0.00 93.33 0.00 97.10 0.00 95.28 0.00 93.86 0.84 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/7.spi_device_stress_all.557857529
95.66 0.11 98.34 0.00 93.55 0.65 98.03 0.00 93.33 0.00 97.10 0.00 95.28 0.00 94.01 0.15 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_errors.2203678799
95.77 0.11 98.34 0.00 93.55 0.00 98.03 0.00 93.33 0.00 97.10 0.00 95.28 0.00 94.75 0.74 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_mode_ignore_cmds.336587096
95.86 0.09 98.40 0.06 93.64 0.09 98.43 0.39 93.33 0.00 97.19 0.08 95.28 0.00 94.75 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/0.spi_device_mem_parity.3289725805
95.94 0.08 98.40 0.00 93.65 0.01 98.43 0.00 93.33 0.00 97.19 0.00 95.28 0.00 95.30 0.54 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_and_tpm_min_idle.4165418681
96.00 0.06 98.40 0.00 93.65 0.00 98.43 0.00 93.33 0.00 97.19 0.00 95.28 0.00 95.74 0.45 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_and_tpm_min_idle.940810141
96.06 0.06 98.40 0.00 93.65 0.00 98.43 0.00 93.33 0.00 97.19 0.00 95.28 0.00 96.14 0.40 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_read_hw_reg.3662432064
96.12 0.06 98.40 0.00 93.65 0.00 98.43 0.00 93.33 0.00 97.19 0.00 95.28 0.00 96.53 0.40 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_all.2813489989
96.17 0.06 98.40 0.00 93.65 0.00 98.43 0.00 93.33 0.00 97.19 0.00 95.42 0.14 96.78 0.25 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/11.spi_device_stress_all.416530042
96.21 0.04 98.40 0.00 93.65 0.00 98.43 0.00 93.33 0.00 97.19 0.00 95.42 0.00 97.08 0.30 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_and_tpm.1348555190
96.26 0.04 98.40 0.00 93.65 0.00 98.43 0.00 93.33 0.00 97.19 0.00 95.42 0.00 97.38 0.30 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_mode_ignore_cmds.628342842
96.30 0.04 98.40 0.00 93.65 0.00 98.43 0.00 93.33 0.00 97.19 0.00 95.42 0.00 97.67 0.30 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/47.spi_device_stress_all.2488132688
96.34 0.04 98.43 0.03 93.69 0.04 98.62 0.20 93.33 0.00 97.19 0.00 95.42 0.00 97.67 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/0.spi_device_alert_test.1469346488
96.37 0.03 98.43 0.00 93.69 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.56 0.14 97.77 0.10 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/16.spi_device_stress_all.4265748148
96.40 0.03 98.43 0.00 93.77 0.09 98.62 0.00 93.33 0.00 97.21 0.02 95.56 0.00 97.87 0.10 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_all.2693671184
96.43 0.03 98.43 0.00 93.77 0.00 98.62 0.00 93.33 0.00 97.21 0.00 95.56 0.00 98.07 0.20 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_mode_ignore_cmds.4076922613
96.45 0.02 98.43 0.00 93.94 0.16 98.62 0.00 93.33 0.00 97.21 0.00 95.56 0.00 98.07 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.587073495
96.47 0.02 98.43 0.00 93.94 0.00 98.62 0.00 93.33 0.00 97.21 0.00 95.56 0.00 98.22 0.15 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_all.2482729719
96.49 0.02 98.43 0.00 93.94 0.00 98.62 0.00 93.33 0.00 97.21 0.00 95.56 0.00 98.37 0.15 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_and_tpm_min_idle.639495889
96.51 0.02 98.43 0.00 93.94 0.00 98.62 0.00 93.33 0.00 97.21 0.00 95.56 0.00 98.51 0.15 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_all.209687928
96.53 0.02 98.43 0.00 93.94 0.00 98.62 0.00 93.33 0.00 97.21 0.00 95.56 0.00 98.66 0.15 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_mode.2460212072
96.55 0.01 98.43 0.00 93.94 0.00 98.62 0.00 93.33 0.00 97.21 0.00 95.56 0.00 98.76 0.10 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_all.771238255
96.56 0.01 98.43 0.00 93.94 0.00 98.62 0.00 93.33 0.00 97.21 0.00 95.56 0.00 98.86 0.10 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/12.spi_device_stress_all.3202509578
96.58 0.01 98.43 0.00 93.94 0.00 98.62 0.00 93.33 0.00 97.21 0.00 95.56 0.00 98.96 0.10 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_and_tpm.2692160903
96.59 0.01 98.43 0.00 93.94 0.00 98.62 0.00 93.33 0.00 97.21 0.00 95.56 0.00 99.06 0.10 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_and_tpm.2244891717
96.60 0.01 98.43 0.00 93.99 0.05 98.62 0.00 93.33 0.00 97.24 0.03 95.56 0.00 99.06 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/27.spi_device_cfg_cmd.1019964555
96.61 0.01 98.43 0.00 94.01 0.02 98.62 0.00 93.33 0.00 97.24 0.00 95.56 0.00 99.11 0.05 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.311213277
96.62 0.01 98.44 0.01 94.02 0.01 98.62 0.00 93.33 0.00 97.27 0.03 95.56 0.00 99.11 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/0.spi_device_pass_addr_payload_swap.1990208643
96.63 0.01 98.44 0.00 94.02 0.00 98.62 0.00 93.33 0.00 97.27 0.00 95.56 0.00 99.16 0.05 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_intg_err.4225925311
96.64 0.01 98.44 0.00 94.02 0.00 98.62 0.00 93.33 0.00 97.27 0.00 95.56 0.00 99.21 0.05 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_mode.475905791
96.64 0.01 98.44 0.00 94.02 0.00 98.62 0.00 93.33 0.00 97.27 0.00 95.56 0.00 99.26 0.05 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_mode_ignore_cmds.881424119
96.65 0.01 98.44 0.00 94.06 0.04 98.62 0.00 93.33 0.00 97.27 0.00 95.56 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_errors.527423976
96.65 0.01 98.44 0.00 94.07 0.01 98.62 0.00 93.33 0.00 97.27 0.00 95.56 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2771231898
96.65 0.01 98.44 0.00 94.08 0.01 98.62 0.00 93.33 0.00 97.27 0.00 95.56 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.502682723

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.3313987742
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3643152470
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1841640328
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.404190977
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.2954839751
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.2161146104
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.4072709845
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.2612158535
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.3382288334
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.4073757241
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1817754703
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1018614389
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.1241904997
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.3339526805
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.1403226774
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.1951533152
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.762286245
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.806614506
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.3836488767
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.2238210719
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3239876841
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.1256166016
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.926515860
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3439612488
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_rw.1885813452
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_intr_test.1651147159
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3682752148
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_intg_err.459716689
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.218371280
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_rw.1745855069
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_intr_test.2919074303
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1647810429
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_errors.330621289
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_intg_err.2593036353
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/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_read_hw_reg.50653496
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_rw.594986149
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.2551589154
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/6.spi_device_upload.471009034
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/7.spi_device_alert_test.2763535931
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/7.spi_device_cfg_cmd.3794867746
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/7.spi_device_csb_read.2108067548
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm.2865027208
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.1156910240
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode.4063777812
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode_ignore_cmds.1516479297
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/7.spi_device_intercept.1484594193
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mailbox.3186217343
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mem_parity.3328709235
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.3297234246
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.3899541229
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.3380993257
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_all.2410976371
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.2338380683
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_rw.1619712137
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.695349091
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/7.spi_device_upload.194658668
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/8.spi_device_alert_test.3719580576
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/8.spi_device_cfg_cmd.2550379219
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/8.spi_device_csb_read.987443744
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_all.3577463398
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.1993495661
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode.4145857688
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.3821995565
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/8.spi_device_intercept.1471153030
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mailbox.4174386159
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mem_parity.1121643778
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.3976455851
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.2889894386
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.2999207597
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_all.904881146
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.2117696300
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_rw.1519357757
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_sts_read.3145094829
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/8.spi_device_upload.3488844168
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/9.spi_device_alert_test.591045203
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/9.spi_device_cfg_cmd.4088351783
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/9.spi_device_csb_read.376420079
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_all.3149958874
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_and_tpm.2305903375
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_and_tpm_min_idle.884646408
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode.1870600250
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.2313967623
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/9.spi_device_intercept.2736729308
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mailbox.2621428055
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mem_parity.3270950113
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.1115115761
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.2109510564
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.1321010049
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/9.spi_device_stress_all.3654537196
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_all.970504664
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.1011291560
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_rw.2173133035
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.1545015504
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/9.spi_device_upload.446632819



Total test records in report: 1150
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/0.spi_device_csb_read.3888822943 Sep 24 02:12:06 PM UTC 24 Sep 24 02:12:08 PM UTC 24 69908220 ps
T2 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/0.spi_device_mem_parity.3289725805 Sep 24 02:12:06 PM UTC 24 Sep 24 02:12:08 PM UTC 24 33193288 ps
T3 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/0.spi_device_ram_cfg.3783386345 Sep 24 02:12:07 PM UTC 24 Sep 24 02:12:09 PM UTC 24 45916437 ps
T4 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_rw.3524716859 Sep 24 02:12:07 PM UTC 24 Sep 24 02:12:10 PM UTC 24 19563497 ps
T5 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_sts_read.4090678759 Sep 24 02:12:07 PM UTC 24 Sep 24 02:12:10 PM UTC 24 272310676 ps
T6 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/0.spi_device_pass_addr_payload_swap.1990208643 Sep 24 02:12:07 PM UTC 24 Sep 24 02:12:12 PM UTC 24 591794214 ps
T7 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/0.spi_device_intercept.4250371315 Sep 24 02:12:08 PM UTC 24 Sep 24 02:12:15 PM UTC 24 130487182 ps
T8 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/0.spi_device_alert_test.1469346488 Sep 24 02:12:16 PM UTC 24 Sep 24 02:12:18 PM UTC 24 44843537 ps
T9 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/0.spi_device_mailbox.3154979359 Sep 24 02:12:08 PM UTC 24 Sep 24 02:12:19 PM UTC 24 1153095997 ps
T10 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/0.spi_device_sec_cm.223323940 Sep 24 02:12:16 PM UTC 24 Sep 24 02:12:19 PM UTC 24 214548754 ps
T11 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_mode.4189610346 Sep 24 02:12:08 PM UTC 24 Sep 24 02:12:20 PM UTC 24 633995626 ps
T12 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/1.spi_device_csb_read.3195881098 Sep 24 02:12:19 PM UTC 24 Sep 24 02:12:21 PM UTC 24 33284274 ps
T25 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/1.spi_device_mem_parity.2335711748 Sep 24 02:12:19 PM UTC 24 Sep 24 02:12:22 PM UTC 24 338954821 ps
T13 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_all.2693671184 Sep 24 02:12:11 PM UTC 24 Sep 24 02:12:23 PM UTC 24 1026193173 ps
T14 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/0.spi_device_read_buffer_direct.3892484848 Sep 24 02:12:10 PM UTC 24 Sep 24 02:12:25 PM UTC 24 1275295536 ps
T15 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_sts_read.228940000 Sep 24 02:12:23 PM UTC 24 Sep 24 02:12:25 PM UTC 24 23786901 ps
T16 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_rw.4053043315 Sep 24 02:12:23 PM UTC 24 Sep 24 02:12:25 PM UTC 24 276572836 ps
T17 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/0.spi_device_cfg_cmd.1591586724 Sep 24 02:12:08 PM UTC 24 Sep 24 02:12:26 PM UTC 24 1408600546 ps
T18 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/0.spi_device_pass_cmd_filtering.1924117993 Sep 24 02:12:07 PM UTC 24 Sep 24 02:12:32 PM UTC 24 3540045722 ps
T19 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_mode.2468591691 Sep 24 02:12:28 PM UTC 24 Sep 24 02:12:34 PM UTC 24 278952566 ps
T20 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/1.spi_device_cfg_cmd.1551453112 Sep 24 02:12:27 PM UTC 24 Sep 24 02:12:34 PM UTC 24 268345992 ps
T44 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/0.spi_device_upload.1198907335 Sep 24 02:12:08 PM UTC 24 Sep 24 02:12:36 PM UTC 24 38728295036 ps
T38 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/1.spi_device_upload.1948473106 Sep 24 02:12:26 PM UTC 24 Sep 24 02:12:36 PM UTC 24 10287465532 ps
T51 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/1.spi_device_intercept.1368700703 Sep 24 02:12:26 PM UTC 24 Sep 24 02:12:37 PM UTC 24 1489145842 ps
T26 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_all.3407885309 Sep 24 02:12:21 PM UTC 24 Sep 24 02:12:38 PM UTC 24 767481213 ps
T52 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/1.spi_device_pass_cmd_filtering.4221806624 Sep 24 02:12:24 PM UTC 24 Sep 24 02:12:39 PM UTC 24 2373632448 ps
T21 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/1.spi_device_sec_cm.3123684797 Sep 24 02:12:38 PM UTC 24 Sep 24 02:12:40 PM UTC 24 153296097 ps
T22 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/1.spi_device_stress_all.2878419426 Sep 24 02:12:38 PM UTC 24 Sep 24 02:12:40 PM UTC 24 176532147 ps
T81 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/1.spi_device_alert_test.3127437671 Sep 24 02:12:39 PM UTC 24 Sep 24 02:12:41 PM UTC 24 14200336 ps
T27 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/2.spi_device_csb_read.3567128076 Sep 24 02:12:40 PM UTC 24 Sep 24 02:12:42 PM UTC 24 17248340 ps
T28 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_read_hw_reg.3917557525 Sep 24 02:12:19 PM UTC 24 Sep 24 02:12:43 PM UTC 24 32162589463 ps
T45 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/1.spi_device_read_buffer_direct.2416196973 Sep 24 02:12:32 PM UTC 24 Sep 24 02:12:44 PM UTC 24 352632240 ps
T29 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_read_hw_reg.3662432064 Sep 24 02:12:07 PM UTC 24 Sep 24 02:12:44 PM UTC 24 6629240851 ps
T41 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/2.spi_device_mem_parity.905640928 Sep 24 02:12:41 PM UTC 24 Sep 24 02:12:44 PM UTC 24 31606066 ps
T30 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.311213277 Sep 24 02:12:11 PM UTC 24 Sep 24 02:12:44 PM UTC 24 46254131695 ps
T83 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_sts_read.1205287569 Sep 24 02:12:42 PM UTC 24 Sep 24 02:12:44 PM UTC 24 61220059 ps
T84 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_rw.1764262138 Sep 24 02:12:43 PM UTC 24 Sep 24 02:12:46 PM UTC 24 40330969 ps
T31 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_all.528027008 Sep 24 02:12:07 PM UTC 24 Sep 24 02:12:47 PM UTC 24 5820929705 ps
T370 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/2.spi_device_pass_cmd_filtering.2472188643 Sep 24 02:12:45 PM UTC 24 Sep 24 02:12:49 PM UTC 24 101434823 ps
T371 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/2.spi_device_cfg_cmd.89484372 Sep 24 02:12:46 PM UTC 24 Sep 24 02:12:51 PM UTC 24 701504208 ps
T42 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_mode_ignore_cmds.1832252375 Sep 24 02:12:09 PM UTC 24 Sep 24 02:12:58 PM UTC 24 6776156877 ps
T94 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_mode.327346263 Sep 24 02:12:47 PM UTC 24 Sep 24 02:13:00 PM UTC 24 396815613 ps
T54 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/2.spi_device_mailbox.2920030441 Sep 24 02:12:45 PM UTC 24 Sep 24 02:13:01 PM UTC 24 1134888806 ps
T53 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/2.spi_device_upload.2444172921 Sep 24 02:12:45 PM UTC 24 Sep 24 02:13:01 PM UTC 24 5315534153 ps
T32 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_and_tpm_min_idle.3164024906 Sep 24 02:12:13 PM UTC 24 Sep 24 02:13:02 PM UTC 24 3437254486 ps
T23 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/2.spi_device_sec_cm.2662610922 Sep 24 02:13:02 PM UTC 24 Sep 24 02:13:04 PM UTC 24 197603254 ps
T82 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/2.spi_device_alert_test.2350873626 Sep 24 02:13:03 PM UTC 24 Sep 24 02:13:05 PM UTC 24 13733454 ps
T372 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/3.spi_device_csb_read.3043001724 Sep 24 02:13:05 PM UTC 24 Sep 24 02:13:07 PM UTC 24 25077066 ps
T48 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_all.500987340 Sep 24 02:12:35 PM UTC 24 Sep 24 02:13:08 PM UTC 24 3673887628 ps
T43 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/3.spi_device_mem_parity.384884146 Sep 24 02:13:06 PM UTC 24 Sep 24 02:13:09 PM UTC 24 46965096 ps
T95 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/2.spi_device_read_buffer_direct.1690172382 Sep 24 02:12:49 PM UTC 24 Sep 24 02:13:09 PM UTC 24 12533123431 ps
T96 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/1.spi_device_mailbox.2079430355 Sep 24 02:12:26 PM UTC 24 Sep 24 02:13:10 PM UTC 24 2636160645 ps
T373 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_read_hw_reg.2186508861 Sep 24 02:13:08 PM UTC 24 Sep 24 02:13:10 PM UTC 24 42512446 ps
T97 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/1.spi_device_pass_addr_payload_swap.2408288746 Sep 24 02:12:26 PM UTC 24 Sep 24 02:13:11 PM UTC 24 6667332396 ps
T91 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_sts_read.1533818411 Sep 24 02:13:09 PM UTC 24 Sep 24 02:13:11 PM UTC 24 47037944 ps
T61 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_rw.1229092587 Sep 24 02:13:10 PM UTC 24 Sep 24 02:13:13 PM UTC 24 366083752 ps
T55 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/2.spi_device_pass_addr_payload_swap.366381132 Sep 24 02:12:45 PM UTC 24 Sep 24 02:13:20 PM UTC 24 12511757378 ps
T79 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/2.spi_device_intercept.2080984068 Sep 24 02:12:45 PM UTC 24 Sep 24 02:13:24 PM UTC 24 2356892488 ps
T92 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_read_hw_reg.2333644187 Sep 24 02:12:41 PM UTC 24 Sep 24 02:13:27 PM UTC 24 42696550951 ps
T62 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_all.4045143927 Sep 24 02:12:42 PM UTC 24 Sep 24 02:13:27 PM UTC 24 15357419031 ps
T226 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/3.spi_device_mailbox.1042867035 Sep 24 02:13:12 PM UTC 24 Sep 24 02:13:28 PM UTC 24 983288850 ps
T102 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/3.spi_device_pass_cmd_filtering.299056485 Sep 24 02:13:11 PM UTC 24 Sep 24 02:13:28 PM UTC 24 9159728015 ps
T374 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_mode.4164065369 Sep 24 02:13:25 PM UTC 24 Sep 24 02:13:31 PM UTC 24 189619223 ps
T80 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/3.spi_device_intercept.3566388318 Sep 24 02:13:12 PM UTC 24 Sep 24 02:13:34 PM UTC 24 895800653 ps
T156 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/3.spi_device_read_buffer_direct.2268717928 Sep 24 02:13:28 PM UTC 24 Sep 24 02:13:35 PM UTC 24 154247521 ps
T63 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_all.3855532006 Sep 24 02:13:09 PM UTC 24 Sep 24 02:13:36 PM UTC 24 2651310817 ps
T299 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/3.spi_device_cfg_cmd.239840311 Sep 24 02:13:21 PM UTC 24 Sep 24 02:13:37 PM UTC 24 3926611749 ps
T375 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/3.spi_device_alert_test.1995524146 Sep 24 02:13:36 PM UTC 24 Sep 24 02:13:39 PM UTC 24 15116632 ps
T24 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/3.spi_device_sec_cm.1631417355 Sep 24 02:13:36 PM UTC 24 Sep 24 02:13:39 PM UTC 24 57036839 ps
T376 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/4.spi_device_csb_read.4052452813 Sep 24 02:13:38 PM UTC 24 Sep 24 02:13:40 PM UTC 24 63601492 ps
T64 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_and_tpm_min_idle.1475104809 Sep 24 02:13:32 PM UTC 24 Sep 24 02:13:40 PM UTC 24 1349220039 ps
T377 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/4.spi_device_mem_parity.281916535 Sep 24 02:13:40 PM UTC 24 Sep 24 02:13:42 PM UTC 24 338375884 ps
T76 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/3.spi_device_upload.536813007 Sep 24 02:13:14 PM UTC 24 Sep 24 02:13:43 PM UTC 24 4413460688 ps
T93 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_sts_read.2694179800 Sep 24 02:13:41 PM UTC 24 Sep 24 02:13:44 PM UTC 24 518122975 ps
T78 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_rw.334087251 Sep 24 02:13:41 PM UTC 24 Sep 24 02:13:47 PM UTC 24 70913964 ps
T378 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/4.spi_device_pass_cmd_filtering.2195039477 Sep 24 02:13:43 PM UTC 24 Sep 24 02:13:49 PM UTC 24 125227891 ps
T301 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/4.spi_device_intercept.3239826575 Sep 24 02:13:44 PM UTC 24 Sep 24 02:13:49 PM UTC 24 115904337 ps
T56 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/3.spi_device_pass_addr_payload_swap.1225774822 Sep 24 02:13:11 PM UTC 24 Sep 24 02:13:51 PM UTC 24 27781391619 ps
T379 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/4.spi_device_mailbox.4141716869 Sep 24 02:13:46 PM UTC 24 Sep 24 02:13:52 PM UTC 24 113739272 ps
T98 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/4.spi_device_cfg_cmd.3831779046 Sep 24 02:13:50 PM UTC 24 Sep 24 02:13:55 PM UTC 24 48316918 ps
T57 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/4.spi_device_pass_addr_payload_swap.1317901089 Sep 24 02:13:44 PM UTC 24 Sep 24 02:13:56 PM UTC 24 1003144445 ps
T46 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/4.spi_device_upload.1101213581 Sep 24 02:13:48 PM UTC 24 Sep 24 02:13:58 PM UTC 24 769958942 ps
T33 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/4.spi_device_stress_all.4235364503 Sep 24 02:13:59 PM UTC 24 Sep 24 02:14:02 PM UTC 24 62839223 ps
T49 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_and_tpm.3924199382 Sep 24 02:13:29 PM UTC 24 Sep 24 02:14:03 PM UTC 24 802556772 ps
T34 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/4.spi_device_sec_cm.378845332 Sep 24 02:14:03 PM UTC 24 Sep 24 02:14:05 PM UTC 24 62559446 ps
T157 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/4.spi_device_read_buffer_direct.4232223939 Sep 24 02:13:52 PM UTC 24 Sep 24 02:14:06 PM UTC 24 3510778502 ps
T179 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_read_hw_reg.2507643749 Sep 24 02:13:40 PM UTC 24 Sep 24 02:14:06 PM UTC 24 9030457266 ps
T180 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/4.spi_device_alert_test.2624118048 Sep 24 02:14:05 PM UTC 24 Sep 24 02:14:07 PM UTC 24 26526841 ps
T181 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/5.spi_device_csb_read.1500286583 Sep 24 02:14:06 PM UTC 24 Sep 24 02:14:08 PM UTC 24 60562586 ps
T182 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/5.spi_device_mem_parity.3590829829 Sep 24 02:14:07 PM UTC 24 Sep 24 02:14:10 PM UTC 24 82758065 ps
T183 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_sts_read.3036620750 Sep 24 02:14:09 PM UTC 24 Sep 24 02:14:11 PM UTC 24 30030136 ps
T184 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_rw.3051056043 Sep 24 02:14:10 PM UTC 24 Sep 24 02:14:13 PM UTC 24 122436378 ps
T35 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/0.spi_device_stress_all.3853631033 Sep 24 02:12:16 PM UTC 24 Sep 24 02:14:15 PM UTC 24 3581338295 ps
T158 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_mode.2178416373 Sep 24 02:13:50 PM UTC 24 Sep 24 02:14:16 PM UTC 24 2367690634 ps
T58 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_mode_ignore_cmds.1186895989 Sep 24 02:12:32 PM UTC 24 Sep 24 02:14:17 PM UTC 24 2893507899 ps
T280 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/5.spi_device_pass_cmd_filtering.1014844647 Sep 24 02:14:12 PM UTC 24 Sep 24 02:14:17 PM UTC 24 277346184 ps
T360 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_all.687160113 Sep 24 02:13:40 PM UTC 24 Sep 24 02:14:18 PM UTC 24 5641208496 ps
T77 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_mode_ignore_cmds.3893348455 Sep 24 02:13:28 PM UTC 24 Sep 24 02:14:20 PM UTC 24 2508476404 ps
T203 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/5.spi_device_cfg_cmd.2382883063 Sep 24 02:14:18 PM UTC 24 Sep 24 02:14:23 PM UTC 24 578723605 ps
T234 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/5.spi_device_intercept.569297719 Sep 24 02:14:16 PM UTC 24 Sep 24 02:14:26 PM UTC 24 227127698 ps
T47 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_and_tpm.673026461 Sep 24 02:12:35 PM UTC 24 Sep 24 02:14:28 PM UTC 24 15727254928 ps
T306 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/5.spi_device_pass_addr_payload_swap.3599972922 Sep 24 02:14:14 PM UTC 24 Sep 24 02:14:28 PM UTC 24 25308102125 ps
T380 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/5.spi_device_alert_test.1111625686 Sep 24 02:14:30 PM UTC 24 Sep 24 02:14:33 PM UTC 24 13224348 ps
T381 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/6.spi_device_csb_read.1203956204 Sep 24 02:14:30 PM UTC 24 Sep 24 02:14:33 PM UTC 24 50852692 ps
T36 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/5.spi_device_stress_all.2970171378 Sep 24 02:14:30 PM UTC 24 Sep 24 02:14:33 PM UTC 24 610612834 ps
T382 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/6.spi_device_mem_parity.2947297622 Sep 24 02:14:33 PM UTC 24 Sep 24 02:14:36 PM UTC 24 120785958 ps
T159 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/5.spi_device_read_buffer_direct.4012929634 Sep 24 02:14:21 PM UTC 24 Sep 24 02:14:37 PM UTC 24 1526073681 ps
T50 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_all.3607281989 Sep 24 02:12:51 PM UTC 24 Sep 24 02:14:37 PM UTC 24 40704902720 ps
T383 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.2551589154 Sep 24 02:14:36 PM UTC 24 Sep 24 02:14:39 PM UTC 24 83549205 ps
T208 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/5.spi_device_mailbox.503557660 Sep 24 02:14:18 PM UTC 24 Sep 24 02:14:39 PM UTC 24 1456395422 ps
T384 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_read_hw_reg.461387111 Sep 24 02:14:07 PM UTC 24 Sep 24 02:14:40 PM UTC 24 29831334258 ps
T186 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_and_tpm_min_idle.771522726 Sep 24 02:12:37 PM UTC 24 Sep 24 02:14:40 PM UTC 24 22190987995 ps
T385 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_rw.594986149 Sep 24 02:14:38 PM UTC 24 Sep 24 02:14:41 PM UTC 24 16891076 ps
T160 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_mode.1362876350 Sep 24 02:14:19 PM UTC 24 Sep 24 02:14:43 PM UTC 24 3405717139 ps
T386 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/6.spi_device_upload.471009034 Sep 24 02:14:41 PM UTC 24 Sep 24 02:14:45 PM UTC 24 40200699 ps
T387 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_read_hw_reg.50653496 Sep 24 02:14:34 PM UTC 24 Sep 24 02:14:45 PM UTC 24 5320208349 ps
T298 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/6.spi_device_cfg_cmd.2770248609 Sep 24 02:14:42 PM UTC 24 Sep 24 02:14:49 PM UTC 24 1012333642 ps
T235 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/6.spi_device_pass_cmd_filtering.2349865743 Sep 24 02:14:38 PM UTC 24 Sep 24 02:14:50 PM UTC 24 6063822557 ps
T263 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/5.spi_device_upload.1277536698 Sep 24 02:14:18 PM UTC 24 Sep 24 02:14:53 PM UTC 24 22576140088 ps
T161 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/6.spi_device_read_buffer_direct.1101939255 Sep 24 02:14:46 PM UTC 24 Sep 24 02:14:53 PM UTC 24 134217383 ps
T388 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/6.spi_device_alert_test.2010417075 Sep 24 02:14:54 PM UTC 24 Sep 24 02:14:56 PM UTC 24 21238517 ps
T389 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/6.spi_device_mailbox.28096723 Sep 24 02:14:41 PM UTC 24 Sep 24 02:14:58 PM UTC 24 1430734228 ps
T390 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/7.spi_device_csb_read.2108067548 Sep 24 02:14:57 PM UTC 24 Sep 24 02:14:59 PM UTC 24 51664681 ps
T391 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mem_parity.3328709235 Sep 24 02:14:59 PM UTC 24 Sep 24 02:15:01 PM UTC 24 25573595 ps
T392 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.2338380683 Sep 24 02:15:00 PM UTC 24 Sep 24 02:15:04 PM UTC 24 303233817 ps
T393 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.695349091 Sep 24 02:15:05 PM UTC 24 Sep 24 02:15:08 PM UTC 24 250463849 ps
T222 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_mode_ignore_cmds.4127674851 Sep 24 02:14:44 PM UTC 24 Sep 24 02:15:08 PM UTC 24 3451689048 ps
T361 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_and_tpm.3678568237 Sep 24 02:14:26 PM UTC 24 Sep 24 02:15:09 PM UTC 24 5900723089 ps
T59 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/6.spi_device_pass_addr_payload_swap.3649348039 Sep 24 02:14:39 PM UTC 24 Sep 24 02:15:09 PM UTC 24 3223561278 ps
T187 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_all.1745665776 Sep 24 02:14:24 PM UTC 24 Sep 24 02:15:10 PM UTC 24 4117713534 ps
T394 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_rw.1619712137 Sep 24 02:15:08 PM UTC 24 Sep 24 02:15:13 PM UTC 24 214742661 ps
T366 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_all.2410976371 Sep 24 02:15:02 PM UTC 24 Sep 24 02:15:15 PM UTC 24 2370963172 ps
T357 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_all.1331564605 Sep 24 02:14:34 PM UTC 24 Sep 24 02:15:18 PM UTC 24 7103583898 ps
T267 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.3899541229 Sep 24 02:15:09 PM UTC 24 Sep 24 02:15:20 PM UTC 24 709621148 ps
T308 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.3297234246 Sep 24 02:15:09 PM UTC 24 Sep 24 02:15:20 PM UTC 24 1027026729 ps
T216 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/7.spi_device_intercept.1484594193 Sep 24 02:15:10 PM UTC 24 Sep 24 02:15:21 PM UTC 24 359028512 ps
T240 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mailbox.3186217343 Sep 24 02:15:11 PM UTC 24 Sep 24 02:15:21 PM UTC 24 224715864 ps
T278 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/6.spi_device_intercept.497399516 Sep 24 02:14:41 PM UTC 24 Sep 24 02:15:22 PM UTC 24 9832676046 ps
T103 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_mode_ignore_cmds.2615034828 Sep 24 02:13:52 PM UTC 24 Sep 24 02:15:23 PM UTC 24 28219530041 ps
T245 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/7.spi_device_upload.194658668 Sep 24 02:15:14 PM UTC 24 Sep 24 02:15:26 PM UTC 24 4700583960 ps
T395 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode.4063777812 Sep 24 02:15:19 PM UTC 24 Sep 24 02:15:29 PM UTC 24 1648651727 ps
T362 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_all.1485768851 Sep 24 02:14:08 PM UTC 24 Sep 24 02:15:29 PM UTC 24 33390579054 ps
T353 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_mode.2808198029 Sep 24 02:14:44 PM UTC 24 Sep 24 02:15:29 PM UTC 24 3784361911 ps
T396 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/7.spi_device_alert_test.2763535931 Sep 24 02:15:27 PM UTC 24 Sep 24 02:15:30 PM UTC 24 38120895 ps
T397 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/8.spi_device_csb_read.987443744 Sep 24 02:15:29 PM UTC 24 Sep 24 02:15:32 PM UTC 24 76238581 ps
T398 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mem_parity.1121643778 Sep 24 02:15:31 PM UTC 24 Sep 24 02:15:33 PM UTC 24 43699945 ps
T399 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_sts_read.3145094829 Sep 24 02:15:33 PM UTC 24 Sep 24 02:15:35 PM UTC 24 23287536 ps
T162 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.3380993257 Sep 24 02:15:21 PM UTC 24 Sep 24 02:15:37 PM UTC 24 948277658 ps
T400 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_rw.1519357757 Sep 24 02:15:34 PM UTC 24 Sep 24 02:15:39 PM UTC 24 139763026 ps
T60 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode_ignore_cmds.1516479297 Sep 24 02:15:21 PM UTC 24 Sep 24 02:15:39 PM UTC 24 1758705683 ps
T321 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.2889894386 Sep 24 02:15:36 PM UTC 24 Sep 24 02:15:41 PM UTC 24 230052682 ps
T204 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/7.spi_device_cfg_cmd.3794867746 Sep 24 02:15:16 PM UTC 24 Sep 24 02:15:42 PM UTC 24 1545406040 ps
T401 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/8.spi_device_upload.3488844168 Sep 24 02:15:40 PM UTC 24 Sep 24 02:15:44 PM UTC 24 277969013 ps
T85 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_mode_ignore_cmds.2038756974 Sep 24 02:12:48 PM UTC 24 Sep 24 02:15:46 PM UTC 24 23312638655 ps
T264 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.3976455851 Sep 24 02:15:38 PM UTC 24 Sep 24 02:15:49 PM UTC 24 387581879 ps
T241 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/8.spi_device_intercept.1471153030 Sep 24 02:15:39 PM UTC 24 Sep 24 02:15:52 PM UTC 24 492160225 ps
T402 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.2117696300 Sep 24 02:15:31 PM UTC 24 Sep 24 02:15:54 PM UTC 24 20434194008 ps
T403 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode.4145857688 Sep 24 02:15:44 PM UTC 24 Sep 24 02:15:54 PM UTC 24 1022647530 ps
T233 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mailbox.4174386159 Sep 24 02:15:40 PM UTC 24 Sep 24 02:15:55 PM UTC 24 1250367954 ps
T404 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/8.spi_device_alert_test.3719580576 Sep 24 02:15:56 PM UTC 24 Sep 24 02:15:58 PM UTC 24 40166446 ps
T405 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.2999207597 Sep 24 02:15:47 PM UTC 24 Sep 24 02:16:00 PM UTC 24 14236760282 ps
T406 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/9.spi_device_csb_read.376420079 Sep 24 02:15:59 PM UTC 24 Sep 24 02:16:01 PM UTC 24 64112513 ps
T99 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/8.spi_device_cfg_cmd.2550379219 Sep 24 02:15:42 PM UTC 24 Sep 24 02:16:02 PM UTC 24 975898809 ps
T407 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mem_parity.3270950113 Sep 24 02:16:01 PM UTC 24 Sep 24 02:16:04 PM UTC 24 187920728 ps
T65 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_and_tpm_min_idle.21952742 Sep 24 02:14:51 PM UTC 24 Sep 24 02:16:05 PM UTC 24 16521815155 ps
T67 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.1011291560 Sep 24 02:16:02 PM UTC 24 Sep 24 02:16:06 PM UTC 24 1248549060 ps
T68 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.1545015504 Sep 24 02:16:05 PM UTC 24 Sep 24 02:16:07 PM UTC 24 17040700 ps
T69 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_rw.2173133035 Sep 24 02:16:07 PM UTC 24 Sep 24 02:16:09 PM UTC 24 38810200 ps
T70 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_all.970504664 Sep 24 02:16:02 PM UTC 24 Sep 24 02:16:10 PM UTC 24 516038830 ps
T71 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_all.1691969473 Sep 24 02:15:22 PM UTC 24 Sep 24 02:16:14 PM UTC 24 9032174509 ps
T72 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_all.904881146 Sep 24 02:15:31 PM UTC 24 Sep 24 02:16:15 PM UTC 24 6758496705 ps
T73 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.2109510564 Sep 24 02:16:07 PM UTC 24 Sep 24 02:16:17 PM UTC 24 339932139 ps
T74 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.1115115761 Sep 24 02:16:08 PM UTC 24 Sep 24 02:16:21 PM UTC 24 2941825907 ps
T75 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_and_tpm_min_idle.3896510035 Sep 24 02:14:27 PM UTC 24 Sep 24 02:16:21 PM UTC 24 58670964220 ps
T100 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/9.spi_device_intercept.2736729308 Sep 24 02:16:10 PM UTC 24 Sep 24 02:16:24 PM UTC 24 617683358 ps
T213 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/9.spi_device_upload.446632819 Sep 24 02:16:14 PM UTC 24 Sep 24 02:16:25 PM UTC 24 430737848 ps
T218 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.2109679918 Sep 24 02:13:01 PM UTC 24 Sep 24 02:16:31 PM UTC 24 19256555889 ps
T190 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_all.3512326901 Sep 24 02:14:46 PM UTC 24 Sep 24 02:16:31 PM UTC 24 25216298918 ps
T408 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode.1870600250 Sep 24 02:16:18 PM UTC 24 Sep 24 02:16:34 PM UTC 24 1971629517 ps
T37 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/9.spi_device_stress_all.3654537196 Sep 24 02:16:32 PM UTC 24 Sep 24 02:16:35 PM UTC 24 63355621 ps
T409 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.1321010049 Sep 24 02:16:23 PM UTC 24 Sep 24 02:16:36 PM UTC 24 995814677 ps
T364 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.1993495661 Sep 24 02:15:55 PM UTC 24 Sep 24 02:16:36 PM UTC 24 18657509966 ps
T410 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/9.spi_device_alert_test.591045203 Sep 24 02:16:34 PM UTC 24 Sep 24 02:16:36 PM UTC 24 43306520 ps
T281 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/9.spi_device_cfg_cmd.4088351783 Sep 24 02:16:16 PM UTC 24 Sep 24 02:16:37 PM UTC 24 1879184511 ps
T411 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/10.spi_device_csb_read.101230437 Sep 24 02:16:36 PM UTC 24 Sep 24 02:16:38 PM UTC 24 30930545 ps
T412 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/10.spi_device_mem_parity.1654901901 Sep 24 02:16:36 PM UTC 24 Sep 24 02:16:39 PM UTC 24 105581822 ps
T413 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_sts_read.1981894267 Sep 24 02:16:38 PM UTC 24 Sep 24 02:16:41 PM UTC 24 15037529 ps
T243 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_all.3149958874 Sep 24 02:16:25 PM UTC 24 Sep 24 02:16:41 PM UTC 24 888195862 ps
T414 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_rw.126493113 Sep 24 02:16:40 PM UTC 24 Sep 24 02:16:43 PM UTC 24 123779531 ps
T191 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.3821995565 Sep 24 02:15:46 PM UTC 24 Sep 24 02:16:45 PM UTC 24 24209002804 ps
T257 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/10.spi_device_pass_cmd_filtering.2485431046 Sep 24 02:16:40 PM UTC 24 Sep 24 02:16:46 PM UTC 24 18875425915 ps
T297 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/10.spi_device_intercept.3564338348 Sep 24 02:16:42 PM UTC 24 Sep 24 02:16:47 PM UTC 24 227570347 ps
T365 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_all.3264988269 Sep 24 02:16:37 PM UTC 24 Sep 24 02:16:47 PM UTC 24 795203818 ps
T309 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/10.spi_device_pass_addr_payload_swap.2702612426 Sep 24 02:16:42 PM UTC 24 Sep 24 02:16:48 PM UTC 24 147307910 ps
T315 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mailbox.2621428055 Sep 24 02:16:11 PM UTC 24 Sep 24 02:16:48 PM UTC 24 3989450454 ps
T415 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_read_hw_reg.785604619 Sep 24 02:16:37 PM UTC 24 Sep 24 02:16:48 PM UTC 24 1990685732 ps
T289 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/10.spi_device_cfg_cmd.2904184700 Sep 24 02:16:47 PM UTC 24 Sep 24 02:16:52 PM UTC 24 121601949 ps
T416 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/10.spi_device_read_buffer_direct.2455564264 Sep 24 02:16:48 PM UTC 24 Sep 24 02:16:55 PM UTC 24 2204510531 ps
T417 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/10.spi_device_alert_test.1262620675 Sep 24 02:16:56 PM UTC 24 Sep 24 02:16:58 PM UTC 24 46209562 ps
T368 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_and_tpm.2577544179 Sep 24 02:16:49 PM UTC 24 Sep 24 02:16:59 PM UTC 24 1152458908 ps
T219 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_and_tpm_min_idle.1090511211 Sep 24 02:13:57 PM UTC 24 Sep 24 02:16:59 PM UTC 24 29025066248 ps
T282 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/10.spi_device_upload.3761559725 Sep 24 02:16:46 PM UTC 24 Sep 24 02:17:00 PM UTC 24 5798746915 ps
T418 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/11.spi_device_csb_read.1768907288 Sep 24 02:16:58 PM UTC 24 Sep 24 02:17:00 PM UTC 24 39211659 ps
T419 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/11.spi_device_mem_parity.3203141672 Sep 24 02:16:59 PM UTC 24 Sep 24 02:17:02 PM UTC 24 27789712 ps
T212 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_all.3116101576 Sep 24 02:13:29 PM UTC 24 Sep 24 02:17:02 PM UTC 24 22961449655 ps
T420 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_sts_read.1084303204 Sep 24 02:17:00 PM UTC 24 Sep 24 02:17:02 PM UTC 24 48645254 ps
T421 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_rw.2703251325 Sep 24 02:17:01 PM UTC 24 Sep 24 02:17:04 PM UTC 24 162473930 ps
T318 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/11.spi_device_pass_cmd_filtering.2191555355 Sep 24 02:17:02 PM UTC 24 Sep 24 02:17:08 PM UTC 24 209004670 ps
T311 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/11.spi_device_pass_addr_payload_swap.3904386528 Sep 24 02:17:03 PM UTC 24 Sep 24 02:17:08 PM UTC 24 244514479 ps
T422 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_read_hw_reg.745093543 Sep 24 02:17:00 PM UTC 24 Sep 24 02:17:15 PM UTC 24 6301927186 ps
T223 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/11.spi_device_upload.1522124002 Sep 24 02:17:09 PM UTC 24 Sep 24 02:17:21 PM UTC 24 591932096 ps
T423 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/11.spi_device_intercept.1183634283 Sep 24 02:17:04 PM UTC 24 Sep 24 02:17:21 PM UTC 24 4031617577 ps
T424 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_mode_ignore_cmds.2563957371 Sep 24 02:17:21 PM UTC 24 Sep 24 02:17:23 PM UTC 24 16514683 ps
T352 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_mode.4100311217 Sep 24 02:17:16 PM UTC 24 Sep 24 02:17:29 PM UTC 24 1632196052 ps
T425 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/11.spi_device_read_buffer_direct.629441706 Sep 24 02:17:22 PM UTC 24 Sep 24 02:17:32 PM UTC 24 7141307148 ps
T426 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_mode.4111112684 Sep 24 02:16:47 PM UTC 24 Sep 24 02:17:32 PM UTC 24 2115397070 ps
T427 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/11.spi_device_alert_test.4244081217 Sep 24 02:17:33 PM UTC 24 Sep 24 02:17:35 PM UTC 24 207838459 ps
T428 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/12.spi_device_csb_read.3943291318 Sep 24 02:17:36 PM UTC 24 Sep 24 02:17:38 PM UTC 24 95348899 ps
T221 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm.2865027208 Sep 24 02:15:22 PM UTC 24 Sep 24 02:17:41 PM UTC 24 9689621748 ps
T288 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/10.spi_device_mailbox.1758428400 Sep 24 02:16:44 PM UTC 24 Sep 24 02:17:41 PM UTC 24 10149646536 ps
T429 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/12.spi_device_mem_parity.1830281527 Sep 24 02:17:39 PM UTC 24 Sep 24 02:17:42 PM UTC 24 118486850 ps
T274 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/11.spi_device_cfg_cmd.2153086344 Sep 24 02:17:09 PM UTC 24 Sep 24 02:17:43 PM UTC 24 3676120148 ps
T430 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_sts_read.3710859325 Sep 24 02:17:42 PM UTC 24 Sep 24 02:17:45 PM UTC 24 36694486 ps
T358 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_all.2482729719 Sep 24 02:17:00 PM UTC 24 Sep 24 02:17:47 PM UTC 24 2161950981 ps
T431 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/12.spi_device_pass_cmd_filtering.2251534482 Sep 24 02:17:45 PM UTC 24 Sep 24 02:17:50 PM UTC 24 111117003 ps
T244 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/12.spi_device_pass_addr_payload_swap.3761614470 Sep 24 02:17:48 PM UTC 24 Sep 24 02:17:53 PM UTC 24 522944082 ps
T432 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_rw.3422219141 Sep 24 02:17:43 PM UTC 24 Sep 24 02:17:55 PM UTC 24 234989744 ps
T433 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/12.spi_device_mailbox.3673871842 Sep 24 02:17:54 PM UTC 24 Sep 24 02:18:01 PM UTC 24 1097727687 ps
T271 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/12.spi_device_upload.2106177137 Sep 24 02:17:57 PM UTC 24 Sep 24 02:18:03 PM UTC 24 1411040758 ps
T86 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/7.spi_device_stress_all.557857529 Sep 24 02:15:24 PM UTC 24 Sep 24 02:18:05 PM UTC 24 53903305947 ps
T237 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/12.spi_device_intercept.218171554 Sep 24 02:17:51 PM UTC 24 Sep 24 02:18:06 PM UTC 24 421679390 ps
T319 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/12.spi_device_cfg_cmd.2872146825 Sep 24 02:18:02 PM UTC 24 Sep 24 02:18:10 PM UTC 24 602290982 ps
T255 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_and_tpm_min_idle.954867149 Sep 24 02:16:49 PM UTC 24 Sep 24 02:18:12 PM UTC 24 34094623738 ps
T359 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_all.1226985614 Sep 24 02:17:42 PM UTC 24 Sep 24 02:18:16 PM UTC 24 4956865725 ps
T188 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_mode_ignore_cmds.2224848321 Sep 24 02:16:48 PM UTC 24 Sep 24 02:18:19 PM UTC 24 4307588076 ps
T434 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_read_hw_reg.1819958406 Sep 24 02:17:41 PM UTC 24 Sep 24 02:18:20 PM UTC 24 11560639524 ps
T435 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/12.spi_device_alert_test.1512968628 Sep 24 02:18:21 PM UTC 24 Sep 24 02:18:23 PM UTC 24 15022279 ps
T436 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/13.spi_device_csb_read.274654873 Sep 24 02:18:21 PM UTC 24 Sep 24 02:18:24 PM UTC 24 45987364 ps
T437 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/12.spi_device_read_buffer_direct.1653918356 Sep 24 02:18:07 PM UTC 24 Sep 24 02:18:24 PM UTC 24 828349924 ps
T438 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/13.spi_device_mem_parity.2999747662 Sep 24 02:18:24 PM UTC 24 Sep 24 02:18:27 PM UTC 24 29177735 ps
T439 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_sts_read.2163745936 Sep 24 02:18:28 PM UTC 24 Sep 24 02:18:30 PM UTC 24 56420077 ps
T440 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_rw.3863570946 Sep 24 02:18:31 PM UTC 24 Sep 24 02:18:33 PM UTC 24 90145094 ps
T441 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_read_hw_reg.1528298430 Sep 24 02:18:24 PM UTC 24 Sep 24 02:18:35 PM UTC 24 1688835498 ps
T189 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/3.spi_device_stress_all.2562165640 Sep 24 02:13:35 PM UTC 24 Sep 24 02:18:42 PM UTC 24 25743200069 ps
T442 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_mode.3544692343 Sep 24 02:18:04 PM UTC 24 Sep 24 02:18:43 PM UTC 24 3039239576 ps
T258 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/13.spi_device_pass_addr_payload_swap.3611952730 Sep 24 02:18:36 PM UTC 24 Sep 24 02:18:48 PM UTC 24 4718689916 ps
T363 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_and_tpm.1056502376 Sep 24 02:12:58 PM UTC 24 Sep 24 02:18:49 PM UTC 24 164679810240 ps
T262 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/11.spi_device_mailbox.657285397 Sep 24 02:17:05 PM UTC 24 Sep 24 02:18:50 PM UTC 24 49315967071 ps
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