Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	36265	1			T6	2		T13	10		T17	8
auto[SpiFlashAddrCfg]	7664	1			T6	4		T7	4		T9	2
auto[SpiFlashAddr3b]	9173	1			T7	2		T13	6		T18	4
auto[SpiFlashAddr4b]	7921	1			T9	2		T11	5		T13	3

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34095

1

T7

6

T9

4

T11

5

auto[1]

26928

1

T6

6

T13

10

T42

40

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32399

1

T6

4

T7

6

T9

2

auto[1]

28624

1

T6

2

T9

2

T11

2

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	40948	1			T6	4		T13	11		T17	8
values[1]	1100	1			T42	2		T32	2		T48	1
values[2]	1487	1			T11	2		T13	4		T38	2
values[3]	1454	1			T42	11		T32	5		T97	2
values[4]	1568	1			T42	7		T53	6		T32	6
values[5]	1391	1			T11	3		T44	2		T42	2
values[6]	1490	1			T7	4		T13	1		T18	2
values[7]	1638	1			T6	2		T13	1		T42	9
values[8]	9947	1			T7	2		T9	4		T13	3

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32213

1

T6

6

T7

6

T9

4

auto[1]

28810

1

T11

5

T13

20

T19

1

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

57739

1

T6

4

T7

6

T9

4

write

3284

1

T6

2

T18

2

T44

2

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19531

1

T6

2

T7

4

T9

2

valids[0x1]

41492

1

T6

4

T7

2

T9

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1643	1			T13	1		T42	1		T53	2
internal_process_ops[0x5a]	1620	1			T18	2		T42	4		T48	1
internal_process_ops[0x05]	22024	1			T13	1		T44	55		T42	6
internal_process_ops[0x35]	1563	1			T13	2		T51	4		T42	4
internal_process_ops[0x15]	1600	1			T6	2		T13	1		T42	4
internal_process_ops[0x03]	1113	1			T9	2		T13	1		T19	1
internal_process_ops[0x0b]	1056	1			T7	2		T11	3		T42	5
internal_process_ops[0x3b]	1076	1			T9	2		T42	1		T32	4
internal_process_ops[0x6b]	1067	1			T42	6		T32	6		T48	1
internal_process_ops[0xbb]	1129	1			T38	2		T52	2		T42	9
internal_process_ops[0xeb]	1097	1			T7	4		T11	2		T44	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

59425

1

T6

4

T7

6

T9

4

auto[1]

1598

1

T6

2

T42

1

T32

8

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58570

1

T6

6

T7

6

T9

4

auto[1]

2453

1

T44

2

T42

3

T32

9

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10808

1

T17

8

T18

4

T20

4

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6991

1

T6

2

T42

10

T32

195

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2130

1

T7

4

T9

2

T18

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1925

1

T6

2

T42

11

T32

5

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2423

1

T7

2

T18

4

T51

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2222

1

T42

6

T32

10

T97

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2200

1

T9

2

T38

2

T42

20

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1836

1

T42

12

T32

7

T97

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

117

1

T44

2

T53

2

T58

5

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

88

1

T32

1

T58

1

T60

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

92

1

T35

1

T58

2

T47

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

125

1

T57

2

T35

2

T58

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

130

1

T18

2

T35

2

T58

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

77

1

T58

3

T47

1

T186

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

79

1

T47

2

T186

1

T85

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

114

1

T6

2

T55

2

T56

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

140

1

T42

1

T32

2

T47

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

92

1

T42

1

T35

1

T47

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

87

1

T42

1

T35

2

T77

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

105

1

T57

2

T77

1

T47

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

120

1

T42

1

T76

2

T47

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

91

1

T32

2

T35

1

T85

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

110

1

T35

1

T77

1

T47

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

111

1

T32

5

T55

2

T85

4

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10032

1

T13

6

T48

6

T49

70

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7649

1

T13

4

T48

31

T49

10

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1408

1

T13

1

T49

5

T158

2

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1380

1

T49

5

T50

12

T187

4

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1945

1

T13

2

T19

1

T48

3

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1741

1

T13

4

T48

2

T49

3

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1527

1

T11

5

T13

1

T48

2

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1522

1

T13

2

T49

6

T50

12

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

109

1

T65

2

T71

8

T75

4

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

75

1

T71

1

T188

1

T189

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

83

1

T187

1

T190

3

T191

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

96

1

T50

4

T65

1

T190

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

97

1

T71

1

T75

4

T190

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

106

1

T103

1

T65

5

T191

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

110

1

T50

3

T65

4

T75

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

108

1

T48

2

T50

1

T65

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

86

1

T49

2

T103

3

T188

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

100

1

T49

1

T50

3

T71

6

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

118

1

T49

1

T50

1

T103

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

114

1

T50

2

T187

1

T190

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

108

1

T48

1

T49

1

T50

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

86

1

T50

1

T103

1

T65

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

100

1

T50

2

T103

2

T190

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

110

1

T65

2

T190

2

T86

2

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3911	1			T17	8		T18	2		T20	4
auto[0]	values[0]	valids[0x1]	16810	1			T6	4		T18	4		T44	61
auto[0]	values[1]	valids[0x1]	611	1			T42	2		T32	2		T102	2
auto[0]	values[2]	valids[0x0]	542	1			T38	2		T42	5		T35	7
auto[0]	values[2]	valids[0x1]	342	1			T42	1		T46	2		T58	7
auto[0]	values[3]	valids[0x0]	558	1			T42	9		T32	3		T35	1
auto[0]	values[3]	valids[0x1]	299	1			T42	2		T32	2		T97	2
auto[0]	values[4]	valids[0x0]	576	1			T42	4		T32	5		T80	4
auto[0]	values[4]	valids[0x1]	310	1			T42	3		T53	6		T32	1
auto[0]	values[5]	valids[0x0]	487	1			T44	2		T42	2		T32	6
auto[0]	values[5]	valids[0x1]	271	1			T32	1		T35	2		T77	2
auto[0]	values[6]	valids[0x0]	545	1			T7	4		T18	2		T51	6
auto[0]	values[6]	valids[0x1]	314	1			T42	2		T58	6		T77	1
auto[0]	values[7]	valids[0x0]	606	1			T6	2		T42	6		T32	1
auto[0]	values[7]	valids[0x1]	356	1			T42	3		T53	4		T57	2
auto[0]	values[8]	valids[0x0]	3554	1			T9	2		T18	2		T44	2
auto[0]	values[8]	valids[0x1]	2121	1			T7	2		T9	2		T18	2
auto[1]	values[0]	valids[0x0]	3990	1			T13	5		T48	4		T49	15
auto[1]	values[0]	valids[0x1]	16237	1			T13	6		T19	1		T48	35
auto[1]	values[1]	valids[0x1]	489	1			T48	1		T50	1		T187	3
auto[1]	values[2]	valids[0x0]	401	1			T11	2		T49	1		T50	5
auto[1]	values[2]	valids[0x1]	202	1			T13	4		T50	2		T103	1
auto[1]	values[3]	valids[0x0]	333	1			T50	1		T187	1		T65	4
auto[1]	values[3]	valids[0x1]	264	1			T49	1		T50	2		T103	3
auto[1]	values[4]	valids[0x0]	395	1			T48	2		T50	4		T187	1
auto[1]	values[4]	valids[0x1]	287	1			T103	5		T65	2		T75	2
auto[1]	values[5]	valids[0x0]	363	1			T49	1		T50	9		T103	3
auto[1]	values[5]	valids[0x1]	270	1			T11	3		T158	1		T50	7
auto[1]	values[6]	valids[0x0]	384	1			T49	1		T103	1		T65	6
auto[1]	values[6]	valids[0x1]	247	1			T13	1		T50	1		T103	2
auto[1]	values[7]	valids[0x0]	396	1			T49	1		T187	1		T65	9
auto[1]	values[7]	valids[0x1]	280	1			T13	1		T49	1		T50	3
auto[1]	values[8]	valids[0x0]	2490	1			T13	2		T48	2		T49	11
auto[1]	values[8]	valids[0x1]	1782	1			T13	1		T48	3		T49	7