Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3246517

1

T6

1

T7

295

T9

468

auto[1]

30119

1

T44

53

T42

55

T32

192

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

815115

1

T6

1

T7

295

T9

468

auto[1]

2461521

1

T13

642

T44

5281

T42

3264

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	611776	1			T6	1		T7	34		T9	105
auto[524288:1048575]	349159	1			T7	31		T11	16		T20	99
auto[1048576:1572863]	415577	1			T7	33		T11	120		T17	1614
auto[1572864:2097151]	341743	1			T7	132		T19	1		T20	48
auto[2097152:2621439]	414468	1			T11	148		T17	2		T20	27
auto[2621440:3145727]	391475	1			T9	124		T13	256		T17	836
auto[3145728:3670015]	390118	1			T7	65		T17	46		T42	179
auto[3670016:4194303]	362320	1			T9	239		T13	3		T17	10

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2497799

1

T6

1

T7

122

T9

7

auto[1]

778837

1

T7

173

T9

461

T11

377

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2840207

1

T6

1

T7

295

T9

468

auto[1]

436429

1

T42

337

T32

3

T48

37

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	161269	1			T6	1		T7	34		T9	105
auto[0]	auto[0]	auto[0:524287]	auto[1]	382067	1			T13	384		T44	5230		T42	256
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	73620	1			T7	31		T11	16		T20	99
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	203100	1			T42	512		T32	1		T48	14
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	72731	1			T7	33		T11	120		T17	1614
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	283499	1			T42	23		T35	512		T58	512
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	94477	1			T7	132		T19	1		T20	48
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	205837	1			T42	1024		T32	3		T80	1
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	79010	1			T11	148		T17	2		T20	27
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	280088	1			T32	257		T35	512		T58	3339
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	102897	1			T9	124		T17	836		T20	3
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	235867	1			T13	256		T42	260		T32	1
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	111735	1			T7	65		T17	46		T42	41
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	218570	1			T42	131		T32	280		T79	1
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	96535	1			T9	239		T13	1		T17	10
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	214861	1			T13	2		T42	768		T32	3509
auto[0]	auto[1]	auto[0:524287]	auto[0]	2402	1			T32	2		T58	8		T77	11
auto[0]	auto[1]	auto[0:524287]	auto[1]	60049	1			T58	1		T77	397		T47	4399
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	2594	1			T42	5		T32	1		T49	6
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	65447	1			T42	256		T48	3		T49	7
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	2785	1			T42	12		T35	1		T58	4
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	53357	1			T35	130		T47	3719		T50	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	630	1			T42	4		T49	4		T35	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	37184	1			T49	2		T50	1		T186	512
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	4297	1			T48	5		T58	26		T47	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	47714	1			T48	2		T49	1		T47	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	625	1			T98	2		T49	1		T58	8
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	48819	1			T50	351		T65	3162		T218	1086
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	4140	1			T42	2		T98	1		T203	4
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	52505	1			T49	512		T50	256		T75	256
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	1455	1			T42	11		T58	9		T47	5
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	46351	1			T47	1		T50	1116		T65	272
auto[1]	auto[0]	auto[0:524287]	auto[0]	515	1			T44	2		T32	2		T76	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	3308	1			T44	51		T32	39		T76	12
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	442	1			T32	1		T47	1		T50	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	3374	1			T32	50		T47	16		T50	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	415	1			T42	3		T47	1		T85	39
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2319	1			T47	15		T85	105		T65	18
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	381	1			T32	3		T35	1		T58	4
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2614	1			T32	82		T47	19		T50	55
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	338	1			T32	1		T77	3		T50	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2359	1			T32	6		T77	265		T50	45
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	431	1			T32	1		T35	2		T50	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2310	1			T32	5		T35	9		T50	39
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	353	1			T42	5		T49	1		T35	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2385	1			T49	43		T35	5		T58	95
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	354	1			T32	1		T49	1		T187	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2146	1			T32	1		T49	2		T187	5
auto[1]	auto[1]	auto[0:524287]	auto[0]	109	1			T58	10		T77	3		T50	2
auto[1]	auto[1]	auto[0:524287]	auto[1]	2057	1			T58	999		T77	371		T50	43
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	74	1			T49	4		T85	2		T190	2
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	508	1			T49	5		T190	83		T189	3
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	72	1			T47	3		T50	1		T103	3
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	399	1			T47	11		T50	9		T190	44
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	93	1			T50	1		T85	5		T65	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	527	1			T50	8		T65	9		T218	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	90	1			T48	2		T58	5		T47	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	572	1			T48	25		T47	32		T65	38
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	86	1			T85	3		T218	1		T189	2
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	440	1			T189	13		T272	51		T273	7
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	71	1			T85	7		T218	1		T188	5
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	359	1			T218	2		T189	1		T87	3
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	89	1			T42	13		T47	1		T50	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	529	1			T42	34		T47	2		T50	14

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2051803	1			T6	1		T7	122		T9	7
auto[0]	auto[0]	auto[1]	764360	1			T7	173		T9	461		T11	377
auto[0]	auto[1]	auto[0]	416578	1			T42	290		T32	3		T48	8
auto[0]	auto[1]	auto[1]	13776	1			T48	2		T203	8		T50	4
auto[1]	auto[0]	auto[0]	23487	1			T44	52		T42	6		T32	192
auto[1]	auto[0]	auto[1]	557	1			T44	1		T42	2		T58	2
auto[1]	auto[1]	auto[0]	5931	1			T42	46		T48	26		T49	9
auto[1]	auto[1]	auto[1]	144	1			T42	1		T48	1		T58	2