Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2421079	1			T1	1		T3	1		T4	22
all_pins[1]	2421079	1			T1	1		T3	1		T4	22
all_pins[2]	2421079	1			T1	1		T3	1		T4	22
all_pins[3]	2421079	1			T1	1		T3	1		T4	22
all_pins[4]	2421079	1			T1	1		T3	1		T4	22
all_pins[5]	2421079	1			T1	1		T3	1		T4	22
all_pins[6]	2421079	1			T1	1		T3	1		T4	22
all_pins[7]	2421079	1			T1	1		T3	1		T4	22

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	19335657	1			T1	8		T3	8		T4	176
values[0x1]	32975	1			T33	49		T35	14		T36	63
transitions[0x0=>0x1]	31105	1			T33	38		T35	11		T36	45
transitions[0x1=>0x0]	31120	1			T33	38		T35	11		T36	46

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2420056	1			T1	1		T3	1		T4	22
all_pins[0]	values[0x1]	1023	1			T33	8		T36	8		T37	2
all_pins[0]	transitions[0x0=>0x1]	609	1			T33	7		T36	5		T37	2
all_pins[0]	transitions[0x1=>0x0]	470	1			T33	4		T35	4		T36	4
all_pins[1]	values[0x0]	2420195	1			T1	1		T3	1		T4	22
all_pins[1]	values[0x1]	884	1			T33	5		T35	4		T36	7
all_pins[1]	transitions[0x0=>0x1]	653	1			T33	2		T35	3		T36	6
all_pins[1]	transitions[0x1=>0x0]	188	1			T33	5		T35	1		T36	4
all_pins[2]	values[0x0]	2420660	1			T1	1		T3	1		T4	22
all_pins[2]	values[0x1]	419	1			T33	8		T35	2		T36	5
all_pins[2]	transitions[0x0=>0x1]	370	1			T33	8		T35	2		T36	3
all_pins[2]	transitions[0x1=>0x0]	196	1			T33	5		T36	12		T37	4
all_pins[3]	values[0x0]	2420834	1			T1	1		T3	1		T4	22
all_pins[3]	values[0x1]	245	1			T33	5		T36	14		T37	5
all_pins[3]	transitions[0x0=>0x1]	191	1			T33	3		T36	12		T37	4
all_pins[3]	transitions[0x1=>0x0]	164	1			T33	6		T36	6		T37	4
all_pins[4]	values[0x0]	2420861	1			T1	1		T3	1		T4	22
all_pins[4]	values[0x1]	218	1			T33	8		T36	8		T37	5
all_pins[4]	transitions[0x0=>0x1]	171	1			T33	7		T36	7		T37	4
all_pins[4]	transitions[0x1=>0x0]	2161	1			T33	3		T35	4		T36	6
all_pins[5]	values[0x0]	2418871	1			T1	1		T3	1		T4	22
all_pins[5]	values[0x1]	2208	1			T33	4		T35	4		T36	7
all_pins[5]	transitions[0x0=>0x1]	1244	1			T33	3		T35	3		T36	4
all_pins[5]	transitions[0x1=>0x0]	26788	1			T33	4		T35	2		T36	4
all_pins[6]	values[0x0]	2393327	1			T1	1		T3	1		T4	22
all_pins[6]	values[0x1]	27752	1			T33	5		T35	3		T36	7
all_pins[6]	transitions[0x0=>0x1]	27692	1			T33	2		T35	2		T36	4
all_pins[6]	transitions[0x1=>0x0]	166	1			T33	3		T36	4		T37	4
all_pins[7]	values[0x0]	2420853	1			T1	1		T3	1		T4	22
all_pins[7]	values[0x1]	226	1			T33	6		T35	1		T36	7
all_pins[7]	transitions[0x0=>0x1]	175	1			T33	6		T35	1		T36	4
all_pins[7]	transitions[0x1=>0x0]	987	1			T33	8		T36	6		T37	1