Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18416

1

T7

6

T9

4

T17

8

auto[1]

13797

1

T6

6

T42

40

T32

222

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4327	1			T42	20		T57	24		T58	20
values[1]	4390	1			T6	6		T20	4		T54	2
values[2]	3728	1			T7	6		T9	4		T42	20
values[3]	3846	1			T38	4		T52	4		T42	20
values[4]	4617	1			T42	20		T32	27		T46	20
values[5]	3388	1			T51	12		T53	24		T35	20
values[6]	4021	1			T17	8		T42	20		T32	20
values[7]	3896	1			T18	12		T44	67		T42	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4177	1			T96	4		T55	20		T79	10
values[1]	4050	1			T7	6		T51	12		T53	24
values[2]	4053	1			T20	4		T42	40		T54	2
values[3]	4095	1			T18	12		T42	20		T57	24
values[4]	4313	1			T42	20		T35	41		T47	60
values[5]	3860	1			T6	6		T9	4		T35	26
values[6]	3699	1			T44	67		T38	4		T52	4
values[7]	3966	1			T17	8		T42	20		T32	40

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	357	1			T274	8		T236	11		T210	10
auto[0]	values[0]	values[1]	307	1			T77	13		T148	7		T275	22
auto[0]	values[0]	values[2]	477	1			T42	12		T235	10		T216	18
auto[0]	values[0]	values[3]	182	1			T85	9		T250	10		T205	18
auto[0]	values[0]	values[4]	248	1			T85	11		T189	12		T39	14
auto[0]	values[0]	values[5]	253	1			T208	8		T85	14		T149	15
auto[0]	values[0]	values[6]	176	1			T58	8		T223	8		T189	5
auto[0]	values[0]	values[7]	561	1			T263	47		T241	8		T212	57
auto[0]	values[1]	values[0]	299	1			T79	10		T212	42		T189	10
auto[0]	values[1]	values[1]	280	1			T32	10		T226	4		T80	6
auto[0]	values[1]	values[2]	331	1			T20	4		T54	2		T85	14
auto[0]	values[1]	values[3]	169	1			T58	10		T250	13		T256	12
auto[0]	values[1]	values[4]	253	1			T47	18		T85	10		T276	13
auto[0]	values[1]	values[5]	263	1			T257	8		T277	31		T230	7
auto[0]	values[1]	values[6]	313	1			T278	8		T279	14		T210	46
auto[0]	values[1]	values[7]	257	1			T76	26		T58	8		T85	8
auto[0]	values[2]	values[0]	261	1			T280	2		T203	28		T222	9
auto[0]	values[2]	values[1]	147	1			T7	6		T102	12		T281	2
auto[0]	values[2]	values[2]	254	1			T282	8		T283	6		T149	14
auto[0]	values[2]	values[3]	334	1			T240	6		T212	14		T87	60
auto[0]	values[2]	values[4]	325	1			T42	11		T35	14		T218	11
auto[0]	values[2]	values[5]	237	1			T9	4		T271	10		T189	12
auto[0]	values[2]	values[6]	303	1			T189	20		T284	2		T144	2
auto[0]	values[2]	values[7]	279	1			T285	4		T220	43		T277	8
auto[0]	values[3]	values[0]	269	1			T96	4		T47	13		T142	17
auto[0]	values[3]	values[1]	228	1			T267	10		T139	11		T220	13
auto[0]	values[3]	values[2]	285	1			T47	36		T212	6		T286	2
auto[0]	values[3]	values[3]	247	1			T58	7		T234	20		T236	14
auto[0]	values[3]	values[4]	342	1			T35	17		T210	9		T139	15
auto[0]	values[3]	values[5]	192	1			T35	19		T225	26		T287	18
auto[0]	values[3]	values[6]	366	1			T38	4		T52	4		T58	22
auto[0]	values[3]	values[7]	184	1			T42	12		T218	7		T288	4
auto[0]	values[4]	values[0]	248	1			T47	9		T87	13		T148	9
auto[0]	values[4]	values[1]	410	1			T58	10		T99	18		T218	41
auto[0]	values[4]	values[2]	290	1			T32	15		T46	20		T85	13
auto[0]	values[4]	values[3]	513	1			T42	16		T58	9		T212	67
auto[0]	values[4]	values[4]	375	1			T212	13		T239	16		T142	9
auto[0]	values[4]	values[5]	301	1			T210	7		T87	12		T142	50
auto[0]	values[4]	values[6]	235	1			T77	11		T186	12		T289	10
auto[0]	values[4]	values[7]	206	1			T39	6		T290	12		T291	2
auto[0]	values[5]	values[0]	192	1			T245	22		T39	11		T260	14
auto[0]	values[5]	values[1]	260	1			T51	12		T53	24		T35	16
auto[0]	values[5]	values[2]	408	1			T243	137		T237	10		T277	26
auto[0]	values[5]	values[3]	226	1			T73	10		T218	25		T262	14
auto[0]	values[5]	values[4]	275	1			T60	12		T39	13		T277	9
auto[0]	values[5]	values[5]	326	1			T47	11		T292	4		T225	54
auto[0]	values[5]	values[6]	153	1			T212	8		T139	19		T142	13
auto[0]	values[5]	values[7]	241	1			T85	11		T189	17		T293	16
auto[0]	values[6]	values[0]	501	1			T85	13		T233	10		T39	82
auto[0]	values[6]	values[1]	238	1			T219	6		T139	10		T142	57
auto[0]	values[6]	values[2]	254	1			T294	14		T295	11		T206	31
auto[0]	values[6]	values[3]	195	1			T35	17		T186	24		T213	16
auto[0]	values[6]	values[4]	390	1			T47	13		T296	8		T87	15
auto[0]	values[6]	values[5]	208	1			T297	4		T39	29		T87	13
auto[0]	values[6]	values[6]	412	1			T42	13		T47	60		T298	10
auto[0]	values[6]	values[7]	280	1			T17	8		T32	14		T299	8
auto[0]	values[7]	values[0]	198	1			T47	27		T243	8		T242	12
auto[0]	values[7]	values[1]	292	1			T204	4		T209	12		T300	20
auto[0]	values[7]	values[2]	195	1			T42	16		T301	4		T87	10
auto[0]	values[7]	values[3]	450	1			T18	12		T77	7		T218	13
auto[0]	values[7]	values[4]	382	1			T100	16		T218	43		T210	67
auto[0]	values[7]	values[5]	204	1			T142	12		T302	14		T230	16
auto[0]	values[7]	values[6]	261	1			T44	67		T186	20		T85	8
auto[0]	values[7]	values[7]	318	1			T32	11		T277	10		T149	22
auto[1]	values[0]	values[0]	250	1			T236	9		T210	10		T148	30
auto[1]	values[0]	values[1]	176	1			T77	7		T303	8		T148	13
auto[1]	values[0]	values[2]	276	1			T42	8		T142	7		T206	11
auto[1]	values[0]	values[3]	171	1			T57	24		T85	11		T304	10
auto[1]	values[0]	values[4]	236	1			T85	9		T189	8		T39	6
auto[1]	values[0]	values[5]	214	1			T85	6		T305	12		T149	5
auto[1]	values[0]	values[6]	122	1			T58	12		T189	26		T248	7
auto[1]	values[0]	values[7]	321	1			T212	5		T39	18		T148	5
auto[1]	values[1]	values[0]	161	1			T74	20		T212	9		T189	10
auto[1]	values[1]	values[1]	526	1			T32	195		T35	3		T85	7
auto[1]	values[1]	values[2]	292	1			T85	6		T218	14		T210	6
auto[1]	values[1]	values[3]	245	1			T58	10		T250	60		T256	8
auto[1]	values[1]	values[4]	189	1			T47	2		T306	12		T85	10
auto[1]	values[1]	values[5]	427	1			T6	6		T277	6		T230	13
auto[1]	values[1]	values[6]	175	1			T210	5		T277	7		T307	6
auto[1]	values[1]	values[7]	210	1			T58	12		T308	4		T85	12
auto[1]	values[2]	values[0]	160	1			T222	11		T85	8		T218	18
auto[1]	values[2]	values[1]	243	1			T264	26		T220	26		T276	18
auto[1]	values[2]	values[2]	170	1			T149	11		T265	9		T266	8
auto[1]	values[2]	values[3]	244	1			T309	6		T212	7		T87	8
auto[1]	values[2]	values[4]	143	1			T42	9		T35	6		T218	9
auto[1]	values[2]	values[5]	234	1			T189	8		T210	8		T220	23
auto[1]	values[2]	values[6]	172	1			T189	7		T209	8		T276	19
auto[1]	values[2]	values[7]	222	1			T220	26		T277	16		T230	7
auto[1]	values[3]	values[0]	267	1			T47	7		T142	10		T148	35
auto[1]	values[3]	values[1]	149	1			T244	8		T139	9		T220	21
auto[1]	values[3]	values[2]	165	1			T47	18		T212	51		T230	14
auto[1]	values[3]	values[3]	385	1			T58	13		T236	65		T209	71
auto[1]	values[3]	values[4]	158	1			T35	4		T210	11		T139	5
auto[1]	values[3]	values[5]	103	1			T35	7		T225	13		T287	2
auto[1]	values[3]	values[6]	377	1			T58	18		T212	6		T258	8
auto[1]	values[3]	values[7]	129	1			T42	8		T97	14		T218	13
auto[1]	values[4]	values[0]	290	1			T47	11		T87	7		T148	62
auto[1]	values[4]	values[1]	265	1			T58	10		T218	10		T210	36
auto[1]	values[4]	values[2]	167	1			T32	12		T85	7		T210	10
auto[1]	values[4]	values[3]	224	1			T42	4		T58	11		T212	3
auto[1]	values[4]	values[4]	405	1			T212	73		T142	11		T265	6
auto[1]	values[4]	values[5]	348	1			T210	67		T87	42		T142	3
auto[1]	values[4]	values[6]	161	1			T77	9		T186	10		T236	14
auto[1]	values[4]	values[7]	179	1			T39	30		T290	8		T261	13
auto[1]	values[5]	values[0]	93	1			T39	13		T214	8		T290	10
auto[1]	values[5]	values[1]	146	1			T35	4		T77	14		T47	10
auto[1]	values[5]	values[2]	137	1			T243	1		T277	24		T310	6
auto[1]	values[5]	values[3]	230	1			T218	22		T311	4		T276	53
auto[1]	values[5]	values[4]	261	1			T60	8		T39	7		T277	11
auto[1]	values[5]	values[5]	150	1			T47	9		T225	13		T312	8
auto[1]	values[5]	values[6]	95	1			T212	12		T139	6		T142	7
auto[1]	values[5]	values[7]	195	1			T85	9		T189	3		T142	11
auto[1]	values[6]	values[0]	397	1			T85	7		T39	12		T87	7
auto[1]	values[6]	values[1]	171	1			T219	15		T139	10		T142	10
auto[1]	values[6]	values[2]	150	1			T295	11		T206	8		T312	36
auto[1]	values[6]	values[3]	83	1			T35	8		T186	12		T269	11
auto[1]	values[6]	values[4]	217	1			T47	27		T87	41		T139	13
auto[1]	values[6]	values[5]	212	1			T59	24		T39	9		T87	31
auto[1]	values[6]	values[6]	176	1			T42	7		T47	10		T85	10
auto[1]	values[6]	values[7]	137	1			T32	6		T35	11		T218	15
auto[1]	values[7]	values[0]	234	1			T55	20		T47	9		T243	24
auto[1]	values[7]	values[1]	212	1			T209	86		T227	12		T256	13
auto[1]	values[7]	values[2]	202	1			T42	4		T87	10		T214	10
auto[1]	values[7]	values[3]	197	1			T77	13		T218	7		T210	9
auto[1]	values[7]	values[4]	114	1			T218	15		T210	15		T313	8
auto[1]	values[7]	values[5]	188	1			T142	8		T314	16		T230	4
auto[1]	values[7]	values[6]	202	1			T56	20		T186	3		T85	12
auto[1]	values[7]	values[7]	247	1			T32	9		T277	66		T149	8