Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	427	1			T7	4		T42	1		T54	2
auto[ReadAddrCrossIntoMailbox]	305	1			T9	2		T32	5		T35	2
auto[ReadAddrCrossOutOfMailbox]	307	1			T42	1		T32	2		T35	1
auto[ReadAddrCrossAllMailbox]	210	1			T9	2		T42	2		T32	3
auto[ReadAddrOutsideMailbox]	3665	1			T7	2		T44	2		T38	2

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2440

1

T7

3

T9

2

T44

1

auto[1]

2474

1

T7

3

T9

2

T44

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	826	1			T9	2		T51	2		T42	3
read_ops[0x0b]	787	1			T7	2		T42	5		T54	2
read_ops[0x3b]	807	1			T9	2		T42	1		T32	4
read_ops[0x6b]	803	1			T42	6		T32	6		T97	2
read_ops[0xbb]	862	1			T38	2		T52	2		T42	9
read_ops[0xeb]	829	1			T7	4		T44	2		T51	6

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	35	1			T240	1		T189	2		T142	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T240	1		T212	1		T247	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T9	1		T58	1		T240	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	31	1			T9	1		T240	1		T87	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	15	1			T47	1		T218	1		T87	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T212	1		T39	1		T139	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T77	1		T85	1		T189	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T236	1		T277	1		T209	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	292	1			T51	1		T42	3		T32	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	330	1			T51	1		T32	1		T102	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	41	1			T54	1		T32	1		T100	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	25	1			T54	1		T100	2		T220	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	31	1			T32	1		T212	2		T262	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T262	1		T142	1		T230	2
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T189	1		T262	1		T39	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T42	1		T262	1		T210	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T77	1		T47	1		T315	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	13	1			T47	1		T315	1		T259	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	307	1			T7	1		T42	1		T32	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	270	1			T7	1		T42	3		T32	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	19	1			T236	1		T249	1		T209	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	44	1			T189	3		T139	1		T220	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	29	1			T32	1		T35	1		T87	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	29	1			T218	1		T189	1		T139	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	19	1			T47	1		T87	2		T225	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	34	1			T35	1		T47	1		T189	2
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T9	1		T42	1		T77	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T9	1		T32	1		T219	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	290	1			T56	2		T35	1		T47	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	311	1			T32	2		T56	2		T35	5
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	41	1			T79	1		T35	1		T234	4
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	44	1			T32	1		T79	1		T234	4
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T32	1		T85	1		T218	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T35	1		T47	1		T219	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T32	1		T85	1		T189	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	19	1			T77	1		T218	1		T210	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T42	1		T259	1		T209	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	11	1			T189	1		T259	1		T210	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	304	1			T42	4		T32	2		T97	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	299	1			T42	1		T32	1		T97	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T234	1		T47	1		T39	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	34	1			T32	1		T58	1		T234	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T47	1		T210	2		T87	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	29	1			T47	1		T219	1		T236	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T47	1		T189	1		T262	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	30	1			T189	1		T262	1		T236	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T32	1		T189	1		T262	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	23	1			T262	1		T220	1		T249	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	335	1			T38	1		T52	1		T42	4
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	310	1			T38	1		T52	1		T42	5
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	34	1			T7	2		T42	1		T58	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	41	1			T7	2		T60	1		T100	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T32	2		T58	2		T77	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T58	1		T189	1		T285	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	33	1			T32	1		T218	1		T243	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T218	1		T212	1		T189	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T32	1		T236	1		T259	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T58	1		T85	1		T189	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	306	1			T44	1		T51	3		T52	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	311	1			T44	1		T51	3		T52	1