Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4135	1			T17	8		T42	20		T32	47
values[1]	3854	1			T18	12		T52	4		T54	2
values[2]	4142	1			T42	40		T76	26		T56	20
values[3]	3716	1			T7	6		T51	12		T42	20
values[4]	4226	1			T9	4		T226	4		T299	8
values[5]	3656	1			T20	4		T42	40		T53	24
values[6]	4212	1			T79	10		T301	4		T58	40
values[7]	4272	1			T6	6		T44	67		T38	4

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4044	1			T51	12		T53	24		T299	8
values[1]	4152	1			T7	6		T44	67		T42	40
values[2]	3646	1			T20	4		T97	14		T35	20
values[3]	4783	1			T54	2		T32	205		T79	10
values[4]	3857	1			T9	4		T18	12		T42	20
values[5]	3953	1			T38	4		T96	4		T35	20
values[6]	3958	1			T42	20		T32	47		T226	4
values[7]	3820	1			T6	6		T17	8		T52	4

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31410

1

T6

4

T7

6

T9

4

auto[1]

803

1

T6

2

T42

1

T32

8

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	559	1			T47	20		T218	18		T237	10
auto[0]	values[0]	values[1]	684	1			T55	16		T102	12		T212	20
auto[0]	values[0]	values[2]	329	1			T203	28		T189	20		T220	29
auto[0]	values[0]	values[3]	564	1			T220	20		T149	18		T316	2
auto[0]	values[0]	values[4]	331	1			T42	19		T277	52		T317	8
auto[0]	values[0]	values[5]	766	1			T35	19		T85	20		T219	21
auto[0]	values[0]	values[6]	437	1			T32	47		T58	20		T318	2
auto[0]	values[0]	values[7]	371	1			T17	8		T282	8		T209	159
auto[0]	values[1]	values[0]	600	1			T289	10		T148	71		T276	31
auto[0]	values[1]	values[1]	525	1			T58	20		T284	2		T307	18
auto[0]	values[1]	values[2]	506	1			T97	14		T35	20		T99	18
auto[0]	values[1]	values[3]	775	1			T54	2		T209	54		T256	16
auto[0]	values[1]	values[4]	360	1			T18	12		T319	10		T220	20
auto[0]	values[1]	values[5]	301	1			T244	6		T250	42		T307	38
auto[0]	values[1]	values[6]	409	1			T35	21		T59	22		T142	58
auto[0]	values[1]	values[7]	277	1			T52	4		T230	17		T290	17
auto[0]	values[2]	values[0]	468	1			T98	12		T85	20		T212	57
auto[0]	values[2]	values[1]	489	1			T42	20		T56	18		T276	78
auto[0]	values[2]	values[2]	237	1			T189	20		T236	17		T209	40
auto[0]	values[2]	values[3]	516	1			T218	20		T212	49		T142	21
auto[0]	values[2]	values[4]	468	1			T76	26		T142	47		T148	36
auto[0]	values[2]	values[5]	473	1			T58	19		T241	8		T239	16
auto[0]	values[2]	values[6]	518	1			T42	20		T235	10		T218	29
auto[0]	values[2]	values[7]	855	1			T35	49		T85	34		T243	32
auto[0]	values[3]	values[0]	272	1			T51	12		T58	20		T218	21
auto[0]	values[3]	values[1]	295	1			T7	6		T213	16		T218	20
auto[0]	values[3]	values[2]	594	1			T58	19		T216	18		T236	19
auto[0]	values[3]	values[3]	668	1			T32	198		T47	23		T212	69
auto[0]	values[3]	values[4]	732	1			T264	24		T218	26		T210	65
auto[0]	values[3]	values[5]	478	1			T96	4		T280	2		T240	6
auto[0]	values[3]	values[6]	332	1			T57	20		T218	38		T87	51
auto[0]	values[3]	values[7]	256	1			T42	20		T47	18		T298	10
auto[0]	values[4]	values[0]	506	1			T299	8		T35	25		T100	16
auto[0]	values[4]	values[1]	597	1			T47	40		T218	19		T142	20
auto[0]	values[4]	values[2]	557	1			T47	33		T267	10		T212	19
auto[0]	values[4]	values[3]	296	1			T85	20		T212	44		T296	8
auto[0]	values[4]	values[4]	542	1			T9	4		T208	8		T186	36
auto[0]	values[4]	values[5]	532	1			T87	55		T320	12		T230	20
auto[0]	values[4]	values[6]	751	1			T226	4		T47	36		T278	8
auto[0]	values[4]	values[7]	333	1			T47	70		T144	2		T148	18
auto[0]	values[5]	values[0]	458	1			T53	24		T77	19		T39	18
auto[0]	values[5]	values[1]	511	1			T42	20		T47	18		T39	38
auto[0]	values[5]	values[2]	304	1			T20	4		T210	20		T87	20
auto[0]	values[5]	values[3]	457	1			T274	8		T210	20		T39	23
auto[0]	values[5]	values[4]	320	1			T186	21		T262	14		T285	4
auto[0]	values[5]	values[5]	518	1			T77	20		T39	36		T87	19
auto[0]	values[5]	values[6]	532	1			T85	19		T297	4		T259	10
auto[0]	values[5]	values[7]	458	1			T42	20		T46	20		T234	20
auto[0]	values[6]	values[0]	376	1			T301	4		T47	20		T321	2
auto[0]	values[6]	values[1]	295	1			T39	20		T87	87		T248	49
auto[0]	values[6]	values[2]	513	1			T212	69		T311	4		T236	21
auto[0]	values[6]	values[3]	885	1			T79	10		T58	20		T186	22
auto[0]	values[6]	values[4]	562	1			T245	22		T85	20		T210	160
auto[0]	values[6]	values[5]	510	1			T58	18		T77	40		T139	20
auto[0]	values[6]	values[6]	465	1			T189	27		T305	12		T139	24
auto[0]	values[6]	values[7]	522	1			T308	4		T218	31		T212	62
auto[0]	values[7]	values[0]	709	1			T85	39		T233	10		T210	25
auto[0]	values[7]	values[1]	659	1			T44	67		T32	19		T35	20
auto[0]	values[7]	values[2]	517	1			T85	19		T189	20		T87	21
auto[0]	values[7]	values[3]	494	1			T212	20		T223	8		T87	22
auto[0]	values[7]	values[4]	446	1			T80	6		T306	12		T322	8
auto[0]	values[7]	values[5]	277	1			T38	4		T263	47		T142	40
auto[0]	values[7]	values[6]	421	1			T58	17		T85	20		T142	40
auto[0]	values[7]	values[7]	642	1			T6	4		T47	20		T222	20
auto[1]	values[0]	values[0]	8	1			T218	2		T225	3		T261	1
auto[1]	values[0]	values[1]	21	1			T55	4		T236	1		T276	1
auto[1]	values[0]	values[2]	6	1			T220	2		T215	2		T323	2
auto[1]	values[0]	values[3]	16	1			T149	2		T207	1		T152	1
auto[1]	values[0]	values[4]	6	1			T42	1		T277	1		T177	1
auto[1]	values[0]	values[5]	22	1			T35	1		T277	3		T225	2
auto[1]	values[0]	values[6]	5	1			T210	1		T149	1		T324	2
auto[1]	values[0]	values[7]	10	1			T209	2		T269	1		T325	1
auto[1]	values[1]	values[0]	13	1			T214	3		T290	2		T326	1
auto[1]	values[1]	values[1]	12	1			T307	2		T225	1		T310	1
auto[1]	values[1]	values[2]	19	1			T309	2		T214	1		T256	1
auto[1]	values[1]	values[3]	21	1			T209	1		T256	4		T206	3
auto[1]	values[1]	values[4]	5	1			T269	1		T327	3		T328	1
auto[1]	values[1]	values[5]	7	1			T244	2		T307	2		T329	2
auto[1]	values[1]	values[6]	13	1			T59	2		T276	2		T225	2
auto[1]	values[1]	values[7]	11	1			T230	3		T290	3		T256	1
auto[1]	values[2]	values[0]	14	1			T189	2		T148	1		T266	1
auto[1]	values[2]	values[1]	9	1			T56	2		T225	3		T330	4
auto[1]	values[2]	values[2]	11	1			T236	3		T215	3		T331	1
auto[1]	values[2]	values[3]	24	1			T212	2		T142	1		T327	2
auto[1]	values[2]	values[4]	11	1			T148	2		T266	1		T332	1
auto[1]	values[2]	values[5]	10	1			T58	1		T149	1		T265	3
auto[1]	values[2]	values[6]	17	1			T218	2		T149	3		T209	2
auto[1]	values[2]	values[7]	22	1			T35	2		T85	6		T210	1
auto[1]	values[3]	values[0]	9	1			T218	3		T256	1		T333	1
auto[1]	values[3]	values[1]	6	1			T314	2		T230	1		T227	3
auto[1]	values[3]	values[2]	17	1			T58	1		T236	1		T276	2
auto[1]	values[3]	values[3]	18	1			T32	7		T212	3		T312	1
auto[1]	values[3]	values[4]	10	1			T264	2		T218	1		T334	2
auto[1]	values[3]	values[5]	12	1			T60	2		T227	1		T334	1
auto[1]	values[3]	values[6]	12	1			T57	4		T87	3		T225	1
auto[1]	values[3]	values[7]	5	1			T47	2		T206	2		T335	1
auto[1]	values[4]	values[0]	11	1			T35	1		T139	3		T276	1
auto[1]	values[4]	values[1]	25	1			T218	1		T250	2		T256	2
auto[1]	values[4]	values[2]	7	1			T212	1		T209	1		T206	4
auto[1]	values[4]	values[3]	5	1			T230	1		T307	1		T336	1
auto[1]	values[4]	values[4]	17	1			T290	1		T312	1		T269	1
auto[1]	values[4]	values[5]	9	1			T87	1		T248	4		T215	1
auto[1]	values[4]	values[6]	19	1			T218	1		T236	1		T248	1
auto[1]	values[4]	values[7]	19	1			T148	2		T149	1		T250	1
auto[1]	values[5]	values[0]	13	1			T77	1		T39	2		T220	1
auto[1]	values[5]	values[1]	12	1			T47	3		T209	1		T230	2
auto[1]	values[5]	values[2]	6	1			T337	2		T334	1		T338	1
auto[1]	values[5]	values[3]	18	1			T39	1		T214	6		T312	2
auto[1]	values[5]	values[4]	16	1			T186	1		T39	4		T149	1
auto[1]	values[5]	values[5]	19	1			T87	1		T142	4		T149	3
auto[1]	values[5]	values[6]	6	1			T85	1		T206	1		T339	1
auto[1]	values[5]	values[7]	8	1			T210	2		T340	1		T341	3
auto[1]	values[6]	values[0]	5	1			T218	2		T148	1		T338	1
auto[1]	values[6]	values[1]	4	1			T87	1		T312	3		-	-
auto[1]	values[6]	values[2]	16	1			T212	1		T236	3		T334	1
auto[1]	values[6]	values[3]	14	1			T186	1		T243	1		T142	3
auto[1]	values[6]	values[4]	15	1			T210	2		T256	1		T342	6
auto[1]	values[6]	values[5]	13	1			T58	2		T277	4		T256	1
auto[1]	values[6]	values[6]	13	1			T189	4		T139	1		T227	5
auto[1]	values[6]	values[7]	4	1			T142	1		T295	2		T343	1
auto[1]	values[7]	values[0]	23	1			T85	1		T210	1		T142	1
auto[1]	values[7]	values[1]	8	1			T32	1		T209	2		T265	1
auto[1]	values[7]	values[2]	7	1			T85	1		T87	2		T209	1
auto[1]	values[7]	values[3]	12	1			T212	1		T220	1		T225	1
auto[1]	values[7]	values[4]	16	1			T265	1		T344	6		T345	2
auto[1]	values[7]	values[5]	6	1			T327	2		T152	1		T346	2
auto[1]	values[7]	values[6]	8	1			T58	3		T327	1		T338	2
auto[1]	values[7]	values[7]	27	1			T6	2		T212	4		T220	2