Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	982	1			T33	27		T35	10		T36	34
all_values[1]	982	1			T33	27		T35	10		T36	34
all_values[2]	982	1			T33	27		T35	10		T36	34
all_values[3]	982	1			T33	27		T35	10		T36	34
all_values[4]	982	1			T33	27		T35	10		T36	34
all_values[5]	982	1			T33	27		T35	10		T36	34
all_values[6]	982	1			T33	27		T35	10		T36	34
all_values[7]	982	1			T33	27		T35	10		T36	34

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4171

1

T33

122

T35

45

T36

130

auto[1]

3685

1

T33

94

T35

35

T36

142

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3157

1

T33

74

T35

26

T36

123

auto[1]

4699

1

T33

142

T35

54

T36

149

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4474

1

T33

117

T35

40

T36

163

auto[1]

3382

1

T33

99

T35

40

T36

109

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	210	1			T33	6		T35	2		T36	9
all_values[0]	auto[0]	auto[0]	auto[1]	84	1			T33	2		T35	3		T37	4
all_values[0]	auto[0]	auto[1]	auto[0]	192	1			T33	2		T35	1		T36	7
all_values[0]	auto[0]	auto[1]	auto[1]	80	1			T33	3		T36	2		T86	1
all_values[0]	auto[1]	auto[0]	auto[1]	249	1			T33	10		T35	4		T36	9
all_values[0]	auto[1]	auto[1]	auto[1]	167	1			T33	4		T36	7		T37	3
all_values[1]	auto[0]	auto[0]	auto[0]	202	1			T33	11		T35	2		T36	3
all_values[1]	auto[0]	auto[0]	auto[1]	78	1			T33	1		T36	4		T37	3
all_values[1]	auto[0]	auto[1]	auto[0]	154	1			T33	3		T35	1		T36	8
all_values[1]	auto[0]	auto[1]	auto[1]	102	1			T33	3		T35	2		T36	4
all_values[1]	auto[1]	auto[0]	auto[1]	234	1			T33	4		T35	2		T36	7
all_values[1]	auto[1]	auto[1]	auto[1]	212	1			T33	5		T35	3		T36	8
all_values[2]	auto[0]	auto[0]	auto[0]	194	1			T33	2		T36	9		T86	7
all_values[2]	auto[0]	auto[0]	auto[1]	89	1			T33	2		T35	1		T36	4
all_values[2]	auto[0]	auto[1]	auto[0]	195	1			T33	4		T35	3		T36	7
all_values[2]	auto[0]	auto[1]	auto[1]	86	1			T33	5		T35	1		T36	1
all_values[2]	auto[1]	auto[0]	auto[1]	219	1			T33	8		T35	3		T36	7
all_values[2]	auto[1]	auto[1]	auto[1]	199	1			T33	6		T35	2		T36	6
all_values[3]	auto[0]	auto[0]	auto[0]	168	1			T33	3		T35	3		T36	5
all_values[3]	auto[0]	auto[0]	auto[1]	120	1			T33	2		T35	1		T36	4
all_values[3]	auto[0]	auto[1]	auto[0]	161	1			T33	4		T35	2		T36	1
all_values[3]	auto[0]	auto[1]	auto[1]	102	1			T33	3		T36	5		T37	1
all_values[3]	auto[1]	auto[0]	auto[1]	221	1			T33	10		T35	2		T36	7
all_values[3]	auto[1]	auto[1]	auto[1]	210	1			T33	5		T35	2		T36	12
all_values[4]	auto[0]	auto[0]	auto[0]	228	1			T33	4		T35	5		T36	8
all_values[4]	auto[0]	auto[0]	auto[1]	94	1			T33	6		T37	1		T86	1
all_values[4]	auto[0]	auto[1]	auto[0]	153	1			T33	1		T35	2		T36	12
all_values[4]	auto[0]	auto[1]	auto[1]	96	1			T33	4		T36	3		T37	2
all_values[4]	auto[1]	auto[0]	auto[1]	202	1			T33	7		T35	3		T36	4
all_values[4]	auto[1]	auto[1]	auto[1]	209	1			T33	5		T36	7		T37	3
all_values[5]	auto[0]	auto[0]	auto[0]	307	1			T33	7		T36	16		T37	6
all_values[5]	auto[0]	auto[1]	auto[0]	243	1			T33	6		T35	3		T36	4
all_values[5]	auto[1]	auto[0]	auto[1]	242	1			T33	9		T35	3		T36	5
all_values[5]	auto[1]	auto[1]	auto[1]	190	1			T33	5		T35	4		T36	9
all_values[6]	auto[0]	auto[0]	auto[0]	183	1			T33	4		T36	7		T185	1
all_values[6]	auto[0]	auto[0]	auto[1]	105	1			T33	3		T35	2		T36	6
all_values[6]	auto[0]	auto[1]	auto[0]	175	1			T33	11		T36	9		T37	2
all_values[6]	auto[0]	auto[1]	auto[1]	96	1			T33	1		T35	2		T36	3
all_values[6]	auto[1]	auto[0]	auto[1]	224	1			T33	1		T35	3		T36	3
all_values[6]	auto[1]	auto[1]	auto[1]	199	1			T33	7		T35	3		T36	6
all_values[7]	auto[0]	auto[0]	auto[0]	213	1			T33	5		T35	1		T36	8
all_values[7]	auto[0]	auto[0]	auto[1]	85	1			T33	7		T36	1		T37	1
all_values[7]	auto[0]	auto[1]	auto[0]	179	1			T33	1		T35	1		T36	10
all_values[7]	auto[0]	auto[1]	auto[1]	100	1			T33	1		T35	2		T36	3
all_values[7]	auto[1]	auto[0]	auto[1]	220	1			T33	8		T35	5		T36	4
all_values[7]	auto[1]	auto[1]	auto[1]	185	1			T33	5		T35	1		T36	8

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal