Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1930

1

T5

5

T15

2

T26

6

auto[1]

1901

1

T5

5

T15

1

T26

5

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1940

1

T26

9

T30

17

T31

23

auto[1]

1891

1

T5

10

T15

3

T26

2

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3098

1

T5

10

T15

3

T26

7

auto[1]

733

1

T26

4

T30

8

T31

8

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	769	1			T5	3		T26	3		T28	5
valid[1]	786	1			T5	1		T15	1		T26	3
valid[2]	759	1			T26	1		T28	10		T29	7
valid[3]	755	1			T5	2		T26	3		T28	11
valid[4]	762	1			T5	4		T15	2		T26	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	116	1			T26	2		T31	1		T62	1
auto[0]	auto[0]	valid[0]	auto[1]	172	1			T5	2		T28	2		T29	5
auto[0]	auto[0]	valid[1]	auto[0]	126	1			T26	1		T30	1		T31	3
auto[0]	auto[0]	valid[1]	auto[1]	215	1			T5	1		T15	1		T28	4
auto[0]	auto[0]	valid[2]	auto[0]	118	1			T30	1		T31	1		T32	1
auto[0]	auto[0]	valid[2]	auto[1]	187	1			T28	4		T29	5		T92	6
auto[0]	auto[0]	valid[3]	auto[0]	121	1			T26	1		T30	1		T31	2
auto[0]	auto[0]	valid[3]	auto[1]	193	1			T28	5		T29	5		T91	2
auto[0]	auto[0]	valid[4]	auto[0]	128	1			T31	3		T62	1		T63	2
auto[0]	auto[0]	valid[4]	auto[1]	177	1			T5	2		T15	1		T28	4
auto[0]	auto[1]	valid[0]	auto[0]	118	1			T30	1		T31	1		T32	2
auto[0]	auto[1]	valid[0]	auto[1]	202	1			T5	1		T26	1		T28	3
auto[0]	auto[1]	valid[1]	auto[0]	121	1			T26	1		T30	1		T31	1
auto[0]	auto[1]	valid[1]	auto[1]	200	1			T26	1		T28	4		T29	2
auto[0]	auto[1]	valid[2]	auto[0]	125	1			T30	1		T31	2		T62	1
auto[0]	auto[1]	valid[2]	auto[1]	177	1			T28	6		T29	2		T92	4
auto[0]	auto[1]	valid[3]	auto[0]	137	1			T31	1		T62	1		T360	2
auto[0]	auto[1]	valid[3]	auto[1]	166	1			T5	2		T28	6		T29	6
auto[0]	auto[1]	valid[4]	auto[0]	97	1			T30	3		T64	1		T357	2
auto[0]	auto[1]	valid[4]	auto[1]	202	1			T5	2		T15	1		T28	3
auto[1]	auto[0]	valid[0]	auto[0]	93	1			T30	1		T31	1		T63	1
auto[1]	auto[0]	valid[1]	auto[0]	62	1			T30	1		T47	1		T362	1
auto[1]	auto[0]	valid[2]	auto[0]	79	1			T31	2		T32	2		T360	1
auto[1]	auto[0]	valid[3]	auto[0]	62	1			T26	1		T30	1		T62	1
auto[1]	auto[0]	valid[4]	auto[0]	81	1			T26	1		T31	1		T32	1
auto[1]	auto[1]	valid[0]	auto[0]	68	1			T30	1		T31	1		T62	2
auto[1]	auto[1]	valid[1]	auto[0]	62	1			T30	1		T360	2		T47	1
auto[1]	auto[1]	valid[2]	auto[0]	73	1			T26	1		T31	1		T62	2
auto[1]	auto[1]	valid[3]	auto[0]	76	1			T26	1		T30	1		T62	2
auto[1]	auto[1]	valid[4]	auto[0]	77	1			T30	2		T31	2		T32	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal