Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47692

1

T4

3

T16

2

T26

141

auto[1]

20374

1

T5

10

T15

3

T26

24

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50576

1

T4

1

T5

10

T15

3

auto[1]

17490

1

T4

2

T26

65

T30

171

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	35047	1			T4	1		T5	10		T15	3
others[1]	5776	1			T26	9		T28	34		T29	35
others[2]	5846	1			T26	11		T28	22		T29	39
others[3]	6544	1			T4	1		T16	1		T26	24
interest[1]	3732	1			T26	10		T28	24		T29	22
interest[4]	22984	1			T4	1		T5	10		T15	3
interest[64]	11121	1			T4	1		T16	1		T26	24

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15513	1			T26	45		T30	174		T31	165
auto[0]	auto[0]	others[1]	2592	1			T26	3		T30	27		T31	29
auto[0]	auto[0]	others[2]	2629	1			T26	4		T30	28		T31	28
auto[0]	auto[0]	others[3]	2865	1			T4	1		T16	1		T26	9
auto[0]	auto[0]	interest[1]	1677	1			T26	5		T30	21		T31	21
auto[0]	auto[0]	interest[4]	10095	1			T26	26		T30	111		T31	116
auto[0]	auto[0]	interest[64]	4926	1			T16	1		T26	10		T30	40
auto[0]	auto[1]	others[0]	10562	1			T5	10		T15	3		T26	10
auto[0]	auto[1]	others[1]	1706	1			T26	1		T28	34		T29	35
auto[0]	auto[1]	others[2]	1709	1			T26	2		T28	22		T29	39
auto[0]	auto[1]	others[3]	1963	1			T26	4		T28	38		T29	40
auto[0]	auto[1]	interest[1]	1111	1			T26	1		T28	24		T29	22
auto[0]	auto[1]	interest[4]	7048	1			T5	10		T15	3		T26	10
auto[0]	auto[1]	interest[64]	3323	1			T26	6		T28	75		T29	69
auto[1]	auto[0]	others[0]	8972	1			T4	1		T26	32		T30	89
auto[1]	auto[0]	others[1]	1478	1			T26	5		T30	13		T31	12
auto[1]	auto[0]	others[2]	1508	1			T26	5		T30	9		T31	12
auto[1]	auto[0]	others[3]	1716	1			T26	11		T30	23		T31	9
auto[1]	auto[0]	interest[1]	944	1			T26	4		T30	14		T31	11
auto[1]	auto[0]	interest[4]	5841	1			T4	1		T26	23		T30	61
auto[1]	auto[0]	interest[64]	2872	1			T4	1		T26	8		T30	23

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal