Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2725191	1			T1	1		T2	1		T3	1
all_values[1]	2725191	1			T1	1		T2	1		T3	1
all_values[2]	2725191	1			T1	1		T2	1		T3	1
all_values[3]	2725191	1			T1	1		T2	1		T3	1
all_values[4]	2725191	1			T1	1		T2	1		T3	1
all_values[5]	2725191	1			T1	1		T2	1		T3	1
all_values[6]	2725191	1			T1	1		T2	1		T3	1
all_values[7]	2725191	1			T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21413621

1

T1

8

T2

8

T3

8

auto[1]

387907

1

T33

13

T36

76

T37

43

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21775197

1

T1

8

T2

8

T3

8

auto[1]

26331

1

T51

2

T33

11

T46

17

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2650458	1			T1	1		T2	1		T3	1
all_values[0]	auto[0]	auto[1]	12353	1			T46	7		T58	62		T82	34
all_values[0]	auto[1]	auto[0]	61708	1			T33	4		T36	6		T37	1
all_values[0]	auto[1]	auto[1]	672	1			T36	2		T37	2		T38	3
all_values[1]	auto[0]	auto[0]	2630139	1			T1	1		T2	1		T3	1
all_values[1]	auto[0]	auto[1]	7761	1			T46	7		T58	62		T42	29
all_values[1]	auto[1]	auto[0]	86619	1			T33	1		T36	11		T37	2
all_values[1]	auto[1]	auto[1]	672	1			T33	1		T36	4		T37	4
all_values[2]	auto[0]	auto[0]	2670389	1			T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	2754	1			T33	4		T46	3		T42	20
all_values[2]	auto[1]	auto[0]	51833	1			T36	9		T37	5		T38	9
all_values[2]	auto[1]	auto[1]	215	1			T36	5		T37	1		T38	1
all_values[3]	auto[0]	auto[0]	2651112	1			T1	1		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	186	1			T33	1		T36	3		T37	1
all_values[3]	auto[1]	auto[0]	73696	1			T33	1		T36	5		T37	5
all_values[3]	auto[1]	auto[1]	197	1			T36	2		T37	3		T38	4
all_values[4]	auto[0]	auto[0]	2668546	1			T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	224	1			T51	2		T36	7		T38	6
all_values[4]	auto[1]	auto[0]	56242	1			T33	2		T36	3		T37	2
all_values[4]	auto[1]	auto[1]	179	1			T36	1		T37	2		T39	4
all_values[5]	auto[0]	auto[0]	2701177	1			T1	1		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	158	1			T36	3		T37	2		T38	3
all_values[5]	auto[1]	auto[0]	23660	1			T36	13		T37	5		T38	7
all_values[5]	auto[1]	auto[1]	196	1			T33	2		T36	3		T37	2
all_values[6]	auto[0]	auto[0]	2715551	1			T1	1		T2	1		T3	1
all_values[6]	auto[0]	auto[1]	198	1			T33	1		T36	8		T37	1
all_values[6]	auto[1]	auto[0]	9251	1			T36	4		T37	4		T38	2
all_values[6]	auto[1]	auto[1]	191	1			T33	1		T37	3		T38	5
all_values[7]	auto[0]	auto[0]	2702440	1			T1	1		T2	1		T3	1
all_values[7]	auto[0]	auto[1]	175	1			T36	5		T37	5		T38	1
all_values[7]	auto[1]	auto[0]	22376	1			T36	4		T37	1		T38	3
all_values[7]	auto[1]	auto[1]	200	1			T33	1		T36	4		T37	1