Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.08 98.44 94.08 98.62 89.36 97.27 95.56 99.26


Total tests in report: 1150
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
60.50 60.50 92.19 92.19 78.38 78.38 59.45 59.45 22.22 22.22 88.62 88.62 72.08 72.08 10.54 10.54 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/0.spi_device_pass_addr_payload_swap.1554374133
70.62 10.12 95.08 2.90 84.52 6.14 61.52 2.07 57.78 35.56 92.60 3.98 79.58 7.50 23.27 12.72 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_and_tpm_min_idle.1041044360
78.06 7.44 95.89 0.81 87.57 3.06 86.12 24.61 77.78 20.00 93.82 1.22 79.58 0.00 25.64 2.38 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/0.spi_device_intercept.3207708051
82.56 4.50 96.30 0.41 88.65 1.08 87.30 1.18 80.00 2.22 94.31 0.49 79.72 0.14 51.63 25.99 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/5.spi_device_stress_all.1948888376
85.94 3.38 97.98 1.68 91.24 2.58 89.67 2.36 86.67 6.67 96.53 2.22 85.00 5.28 54.50 2.87 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_all.1998093628
87.91 1.97 98.09 0.11 91.56 0.32 89.67 0.00 91.11 4.44 96.77 0.24 85.00 0.00 63.17 8.66 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_and_tpm.80625688
89.42 1.51 98.09 0.00 91.69 0.12 90.06 0.39 91.11 0.00 96.80 0.03 93.47 8.47 64.70 1.53 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2555138505
90.60 1.18 98.13 0.04 91.76 0.07 90.06 0.00 93.33 2.22 96.83 0.03 93.47 0.00 70.59 5.89 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_mode_ignore_cmds.3112809974
91.49 0.89 98.13 0.00 91.80 0.04 91.14 1.08 93.33 0.00 96.83 0.00 93.61 0.14 75.59 5.00 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/0.spi_device_stress_all.1101706829
92.17 0.68 98.14 0.01 91.80 0.00 95.87 4.72 93.33 0.00 96.83 0.00 93.61 0.00 75.59 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/0.spi_device_ram_cfg.377216558
92.83 0.66 98.14 0.00 91.80 0.00 95.87 0.00 93.33 0.00 96.83 0.00 93.61 0.00 80.25 4.65 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/4.spi_device_stress_all.3547210871
93.26 0.43 98.14 0.00 91.80 0.00 95.87 0.00 93.33 0.00 96.83 0.00 93.61 0.00 83.27 3.02 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_and_tpm_min_idle.2844031470
93.64 0.38 98.15 0.01 91.86 0.06 98.03 2.17 93.33 0.00 96.85 0.02 93.75 0.14 83.51 0.25 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/0.spi_device_sec_cm.4027044216
93.97 0.33 98.15 0.00 91.90 0.04 98.03 0.00 93.33 0.00 96.85 0.00 93.75 0.00 85.79 2.28 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.2926124046
94.27 0.30 98.27 0.12 92.74 0.85 98.03 0.00 93.33 0.00 97.02 0.17 94.44 0.69 86.04 0.25 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_mode.3758508236
94.51 0.24 98.30 0.03 92.78 0.04 98.03 0.00 93.33 0.00 97.09 0.07 94.44 0.00 87.57 1.53 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_and_tpm_min_idle.3818052888
94.68 0.17 98.30 0.00 93.62 0.85 98.03 0.00 93.33 0.00 97.09 0.00 94.44 0.00 87.92 0.35 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_errors.2575538194
94.83 0.16 98.30 0.00 93.62 0.00 98.03 0.00 93.33 0.00 97.09 0.00 94.44 0.00 89.01 1.09 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/16.spi_device_stress_all.2437188260
94.98 0.15 98.31 0.01 93.66 0.04 98.03 0.00 93.33 0.00 97.10 0.02 94.44 0.00 90.00 0.99 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.699537000
95.13 0.15 98.32 0.01 93.66 0.00 98.03 0.00 93.33 0.00 97.12 0.02 94.44 0.00 90.99 0.99 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_mode_ignore_cmds.619308093
95.27 0.14 98.32 0.00 93.66 0.00 98.03 0.00 93.33 0.00 97.12 0.00 95.42 0.97 90.99 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.3750284724
95.40 0.13 98.32 0.00 93.67 0.01 98.03 0.00 93.33 0.00 97.12 0.00 95.42 0.00 91.88 0.89 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_read_hw_reg.1387255973
95.52 0.12 98.32 0.00 93.67 0.00 98.03 0.00 93.33 0.00 97.12 0.00 95.42 0.00 92.72 0.84 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.4042150287
95.62 0.10 98.32 0.00 93.76 0.09 98.03 0.00 93.33 0.00 97.12 0.00 95.42 0.00 93.37 0.64 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_all.135949879
95.71 0.09 98.32 0.00 93.76 0.00 98.03 0.00 93.33 0.00 97.12 0.00 95.42 0.00 94.01 0.64 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/1.spi_device_stress_all.2111183060
95.80 0.09 98.37 0.06 93.85 0.09 98.43 0.39 93.33 0.00 97.21 0.08 95.42 0.00 94.01 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/0.spi_device_mem_parity.2047728213
95.89 0.08 98.37 0.00 93.85 0.00 98.43 0.00 93.33 0.00 97.21 0.00 95.42 0.00 94.60 0.59 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/18.spi_device_stress_all.1792764035
95.96 0.08 98.37 0.00 93.85 0.00 98.43 0.00 93.33 0.00 97.21 0.00 95.42 0.00 95.15 0.54 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_all.3555857446
96.03 0.07 98.37 0.00 93.85 0.00 98.43 0.00 93.33 0.00 97.21 0.00 95.42 0.00 95.64 0.50 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_and_tpm_min_idle.927132743
96.10 0.06 98.37 0.00 93.85 0.00 98.43 0.00 93.33 0.00 97.21 0.00 95.42 0.00 96.09 0.45 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_all.1188862314
96.15 0.05 98.37 0.00 93.85 0.00 98.43 0.00 93.33 0.00 97.21 0.00 95.42 0.00 96.44 0.35 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_and_tpm.3921108501
96.20 0.05 98.37 0.00 93.87 0.02 98.43 0.00 93.33 0.00 97.22 0.02 95.42 0.00 96.73 0.30 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_mode_ignore_cmds.2797369431
96.24 0.04 98.37 0.00 93.87 0.00 98.43 0.00 93.33 0.00 97.22 0.00 95.42 0.00 97.03 0.30 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm.2228456898
96.28 0.04 98.40 0.03 93.91 0.04 98.62 0.20 93.33 0.00 97.22 0.00 95.42 0.00 97.03 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/0.spi_device_alert_test.1990178319
96.31 0.04 98.40 0.00 93.91 0.00 98.62 0.00 93.33 0.00 97.22 0.00 95.42 0.00 97.28 0.25 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_and_tpm_min_idle.2440257343
96.35 0.04 98.40 0.00 93.91 0.00 98.62 0.00 93.33 0.00 97.22 0.00 95.42 0.00 97.52 0.25 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/9.spi_device_stress_all.4149434778
96.38 0.03 98.40 0.00 93.91 0.00 98.62 0.00 93.33 0.00 97.22 0.00 95.42 0.00 97.72 0.20 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_mode_ignore_cmds.3021482847
96.40 0.03 98.40 0.00 93.91 0.00 98.62 0.00 93.33 0.00 97.22 0.00 95.56 0.14 97.77 0.05 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/30.spi_device_stress_all.2204396118
96.42 0.02 98.40 0.00 93.91 0.00 98.62 0.00 93.33 0.00 97.22 0.00 95.56 0.00 97.92 0.15 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_and_tpm.3755089345
96.44 0.02 98.40 0.00 93.91 0.00 98.62 0.00 93.33 0.00 97.22 0.00 95.56 0.00 98.07 0.15 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_mode.2149819380
96.46 0.02 98.40 0.00 93.97 0.06 98.62 0.00 93.33 0.00 97.22 0.00 95.56 0.00 98.12 0.05 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_errors.2296865513
96.48 0.02 98.40 0.00 93.99 0.01 98.62 0.00 93.33 0.00 97.22 0.00 95.56 0.00 98.22 0.10 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/4.spi_device_upload.3409635124
96.49 0.01 98.40 0.00 93.99 0.00 98.62 0.00 93.33 0.00 97.22 0.00 95.56 0.00 98.32 0.10 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_intg_err.2001544833
96.50 0.01 98.40 0.00 93.99 0.00 98.62 0.00 93.33 0.00 97.22 0.00 95.56 0.00 98.42 0.10 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_all.1556682517
96.52 0.01 98.40 0.00 93.99 0.00 98.62 0.00 93.33 0.00 97.22 0.00 95.56 0.00 98.51 0.10 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_and_tpm_min_idle.1388245317
96.53 0.01 98.40 0.00 93.99 0.00 98.62 0.00 93.33 0.00 97.22 0.00 95.56 0.00 98.61 0.10 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_and_tpm_min_idle.2278015870
96.55 0.01 98.40 0.00 93.99 0.00 98.62 0.00 93.33 0.00 97.22 0.00 95.56 0.00 98.71 0.10 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.354949614
96.56 0.01 98.40 0.00 93.99 0.00 98.62 0.00 93.33 0.00 97.22 0.00 95.56 0.00 98.81 0.10 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_all.4097940914
96.57 0.01 98.40 0.00 94.02 0.04 98.62 0.00 93.33 0.00 97.24 0.02 95.56 0.00 98.81 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/4.spi_device_cfg_cmd.2749847338
96.58 0.01 98.40 0.00 94.02 0.00 98.62 0.00 93.33 0.00 97.24 0.00 95.56 0.00 98.86 0.05 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_intg_err.2733969738
96.58 0.01 98.40 0.00 94.02 0.00 98.62 0.00 93.33 0.00 97.24 0.00 95.56 0.00 98.91 0.05 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_intg_err.830388601
96.59 0.01 98.40 0.00 94.02 0.00 98.62 0.00 93.33 0.00 97.24 0.00 95.56 0.00 98.96 0.05 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_mode_ignore_cmds.4252311412
96.60 0.01 98.40 0.00 94.02 0.00 98.62 0.00 93.33 0.00 97.24 0.00 95.56 0.00 99.01 0.05 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_mode.924284456
96.60 0.01 98.40 0.00 94.02 0.00 98.62 0.00 93.33 0.00 97.24 0.00 95.56 0.00 99.06 0.05 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_mode.3348749062
96.61 0.01 98.40 0.00 94.02 0.00 98.62 0.00 93.33 0.00 97.24 0.00 95.56 0.00 99.11 0.05 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_and_tpm_min_idle.2152895340
96.62 0.01 98.40 0.00 94.02 0.00 98.62 0.00 93.33 0.00 97.24 0.00 95.56 0.00 99.16 0.05 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/25.spi_device_stress_all.888770502
96.63 0.01 98.40 0.00 94.02 0.00 98.62 0.00 93.33 0.00 97.24 0.00 95.56 0.00 99.21 0.05 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/44.spi_device_stress_all.1746386845
96.63 0.01 98.40 0.00 94.02 0.00 98.62 0.00 93.33 0.00 97.24 0.00 95.56 0.00 99.26 0.05 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_mode_ignore_cmds.573382627
96.64 0.01 98.42 0.02 94.05 0.02 98.62 0.00 93.33 0.00 97.24 0.00 95.56 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/0.spi_device_csb_read.1406480521
96.64 0.01 98.43 0.01 94.05 0.00 98.62 0.00 93.33 0.00 97.26 0.02 95.56 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/0.spi_device_pass_cmd_filtering.3876703030
96.65 0.01 98.44 0.01 94.05 0.00 98.62 0.00 93.33 0.00 97.27 0.02 95.56 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/0.spi_device_read_buffer_direct.1242742217
96.65 0.01 98.44 0.00 94.07 0.02 98.62 0.00 93.33 0.00 97.27 0.00 95.56 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.111192541
96.65 0.01 98.44 0.00 94.08 0.01 98.62 0.00 93.33 0.00 97.27 0.00 95.56 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.298085633

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.1201165762
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.999896227
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.4175537862
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.2217895351
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.4273422342
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.3665747216
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.147276830
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.2613455923
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.389551433
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.835583211
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2694521772
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.1705945144
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.1349959181
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.4190370603
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.1792993714
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2335542876
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.2633943538
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3738293385
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.3083556863
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.1847462122
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/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_all.2827267521
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/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_rw.2620579279
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.3883921290
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/6.spi_device_upload.304129638
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/7.spi_device_alert_test.796870772
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/7.spi_device_cfg_cmd.2572814853
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/7.spi_device_csb_read.1964801610
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_all.262935300
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm.626812353
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode.4153779700
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode_ignore_cmds.826555247
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/7.spi_device_intercept.3053773092
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mailbox.2368183122
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mem_parity.2036868031
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.3307494111
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.3816837313
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.2894517925
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/7.spi_device_stress_all.3646179006
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_all.2357607211
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.1557839875
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_rw.277017187
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.3730973624
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/7.spi_device_upload.1443485773
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/8.spi_device_alert_test.2582520505
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/8.spi_device_cfg_cmd.464046327
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/8.spi_device_csb_read.1024566208
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_all.845581998
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.2264277302
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode.3116322170
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/8.spi_device_intercept.2249813891
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mailbox.2505343669
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mem_parity.441962579
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.2880789516
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.831997061
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.1453431263
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/8.spi_device_stress_all.582974737
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_all.4108480540
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.3073821322
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_rw.2354350562
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_sts_read.2926834380
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/8.spi_device_upload.1745830451
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/9.spi_device_alert_test.2984094824
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/9.spi_device_cfg_cmd.3952792396
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/9.spi_device_csb_read.3065207531
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_all.3049410303
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_and_tpm_min_idle.3494221951
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode.3087519854
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/9.spi_device_intercept.3062008270
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mailbox.1128469408
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mem_parity.584145488
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.2632761979
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.1292445483
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.752640380
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_all.200089418
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.4100160913
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_rw.2481762605
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.2439127482
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/9.spi_device_upload.4128337835



Total test records in report: 1150
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/0.spi_device_ram_cfg.377216558 Oct 03 04:21:23 AM UTC 24 Oct 03 04:21:25 AM UTC 24 19735962 ps
T2 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/0.spi_device_csb_read.1406480521 Oct 03 04:21:23 AM UTC 24 Oct 03 04:21:26 AM UTC 24 123314138 ps
T3 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_sts_read.3087006348 Oct 03 04:21:24 AM UTC 24 Oct 03 04:21:26 AM UTC 24 29694468 ps
T4 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_rw.1142764786 Oct 03 04:21:24 AM UTC 24 Oct 03 04:21:26 AM UTC 24 123572406 ps
T5 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/0.spi_device_mem_parity.2047728213 Oct 03 04:21:23 AM UTC 24 Oct 03 04:21:26 AM UTC 24 45619907 ps
T6 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/0.spi_device_pass_addr_payload_swap.1554374133 Oct 03 04:21:24 AM UTC 24 Oct 03 04:21:27 AM UTC 24 92485950 ps
T7 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_mode_ignore_cmds.1400961849 Oct 03 04:21:26 AM UTC 24 Oct 03 04:21:29 AM UTC 24 42949076 ps
T8 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/1.spi_device_csb_read.1841664480 Oct 03 04:21:27 AM UTC 24 Oct 03 04:21:29 AM UTC 24 50202380 ps
T9 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/0.spi_device_alert_test.1990178319 Oct 03 04:21:27 AM UTC 24 Oct 03 04:21:29 AM UTC 24 45588927 ps
T10 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/1.spi_device_mem_parity.1826156288 Oct 03 04:21:27 AM UTC 24 Oct 03 04:21:30 AM UTC 24 26948505 ps
T11 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/0.spi_device_sec_cm.4027044216 Oct 03 04:21:27 AM UTC 24 Oct 03 04:21:30 AM UTC 24 163019120 ps
T12 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_all.1998093628 Oct 03 04:21:24 AM UTC 24 Oct 03 04:21:30 AM UTC 24 665340007 ps
T13 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_mode.2084385676 Oct 03 04:21:26 AM UTC 24 Oct 03 04:21:30 AM UTC 24 111257654 ps
T14 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/0.spi_device_pass_cmd_filtering.3876703030 Oct 03 04:21:24 AM UTC 24 Oct 03 04:21:30 AM UTC 24 4019201659 ps
T15 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_sts_read.688388940 Oct 03 04:21:28 AM UTC 24 Oct 03 04:21:30 AM UTC 24 40545172 ps
T16 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_rw.519552571 Oct 03 04:21:28 AM UTC 24 Oct 03 04:21:31 AM UTC 24 13475923 ps
T17 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_read_hw_reg.4226856492 Oct 03 04:21:27 AM UTC 24 Oct 03 04:21:32 AM UTC 24 28135548310 ps
T18 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/0.spi_device_intercept.3207708051 Oct 03 04:21:24 AM UTC 24 Oct 03 04:21:33 AM UTC 24 971313320 ps
T19 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/0.spi_device_read_buffer_direct.1242742217 Oct 03 04:21:26 AM UTC 24 Oct 03 04:21:34 AM UTC 24 485708847 ps
T40 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_mode_ignore_cmds.2874047476 Oct 03 04:21:31 AM UTC 24 Oct 03 04:21:35 AM UTC 24 98690789 ps
T20 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/1.spi_device_pass_addr_payload_swap.3643282790 Oct 03 04:21:29 AM UTC 24 Oct 03 04:21:35 AM UTC 24 2776876990 ps
T100 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/1.spi_device_alert_test.846945571 Oct 03 04:21:34 AM UTC 24 Oct 03 04:21:36 AM UTC 24 51189729 ps
T21 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/1.spi_device_intercept.4044531067 Oct 03 04:21:29 AM UTC 24 Oct 03 04:21:36 AM UTC 24 154400184 ps
T22 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/2.spi_device_csb_read.1542957167 Oct 03 04:21:34 AM UTC 24 Oct 03 04:21:36 AM UTC 24 18205315 ps
T31 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/1.spi_device_sec_cm.2872960320 Oct 03 04:21:34 AM UTC 24 Oct 03 04:21:37 AM UTC 24 334120131 ps
T27 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_sts_read.1750739564 Oct 03 04:21:35 AM UTC 24 Oct 03 04:21:37 AM UTC 24 15709996 ps
T28 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_read_hw_reg.1387255973 Oct 03 04:21:23 AM UTC 24 Oct 03 04:21:38 AM UTC 24 3049241995 ps
T45 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/2.spi_device_mem_parity.143291912 Oct 03 04:21:35 AM UTC 24 Oct 03 04:21:38 AM UTC 24 26553437 ps
T23 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/1.spi_device_cfg_cmd.4240230798 Oct 03 04:21:30 AM UTC 24 Oct 03 04:21:39 AM UTC 24 219370457 ps
T24 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/1.spi_device_upload.1525651218 Oct 03 04:21:30 AM UTC 24 Oct 03 04:21:40 AM UTC 24 1518421706 ps
T29 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_rw.321711927 Oct 03 04:21:36 AM UTC 24 Oct 03 04:21:40 AM UTC 24 111862620 ps
T25 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/1.spi_device_read_buffer_direct.1186560516 Oct 03 04:21:31 AM UTC 24 Oct 03 04:21:40 AM UTC 24 232526873 ps
T26 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/0.spi_device_upload.1213142125 Oct 03 04:21:26 AM UTC 24 Oct 03 04:21:41 AM UTC 24 11056311770 ps
T30 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_read_hw_reg.3318151666 Oct 03 04:21:35 AM UTC 24 Oct 03 04:21:43 AM UTC 24 922491040 ps
T61 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/2.spi_device_cfg_cmd.1035989953 Oct 03 04:21:39 AM UTC 24 Oct 03 04:21:44 AM UTC 24 38423160 ps
T60 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/0.spi_device_mailbox.4056575449 Oct 03 04:21:24 AM UTC 24 Oct 03 04:21:45 AM UTC 24 1109859229 ps
T32 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/2.spi_device_sec_cm.664854332 Oct 03 04:21:42 AM UTC 24 Oct 03 04:21:45 AM UTC 24 94181357 ps
T59 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/2.spi_device_pass_addr_payload_swap.1015751962 Oct 03 04:21:37 AM UTC 24 Oct 03 04:21:45 AM UTC 24 523795886 ps
T48 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_all.2691315889 Oct 03 04:21:35 AM UTC 24 Oct 03 04:21:45 AM UTC 24 3146512222 ps
T98 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/2.spi_device_alert_test.1649534492 Oct 03 04:21:43 AM UTC 24 Oct 03 04:21:46 AM UTC 24 28799560 ps
T51 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_mode.3758508236 Oct 03 04:21:31 AM UTC 24 Oct 03 04:21:47 AM UTC 24 639345691 ps
T403 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/3.spi_device_csb_read.1680413924 Oct 03 04:21:44 AM UTC 24 Oct 03 04:21:47 AM UTC 24 22772415 ps
T64 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/2.spi_device_upload.2440724124 Oct 03 04:21:38 AM UTC 24 Oct 03 04:21:47 AM UTC 24 1403234936 ps
T49 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/3.spi_device_mem_parity.144570217 Oct 03 04:21:45 AM UTC 24 Oct 03 04:21:47 AM UTC 24 25112787 ps
T41 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_mode.1033698073 Oct 03 04:21:39 AM UTC 24 Oct 03 04:21:48 AM UTC 24 750698366 ps
T404 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_sts_read.2394929915 Oct 03 04:21:46 AM UTC 24 Oct 03 04:21:48 AM UTC 24 11932931 ps
T62 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/1.spi_device_pass_cmd_filtering.2050835957 Oct 03 04:21:29 AM UTC 24 Oct 03 04:21:49 AM UTC 24 19104908558 ps
T50 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_rw.347447898 Oct 03 04:21:46 AM UTC 24 Oct 03 04:21:49 AM UTC 24 89907149 ps
T63 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/2.spi_device_intercept.3517901742 Oct 03 04:21:38 AM UTC 24 Oct 03 04:21:50 AM UTC 24 2808775936 ps
T123 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/4.spi_device_intercept.2834461822 Oct 03 04:21:59 AM UTC 24 Oct 03 04:22:04 AM UTC 24 95747740 ps
T94 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/2.spi_device_mailbox.2903050682 Oct 03 04:21:38 AM UTC 24 Oct 03 04:21:51 AM UTC 24 326797740 ps
T139 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/2.spi_device_pass_cmd_filtering.1982648572 Oct 03 04:21:36 AM UTC 24 Oct 03 04:21:51 AM UTC 24 1419336856 ps
T52 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/2.spi_device_read_buffer_direct.1812671018 Oct 03 04:21:41 AM UTC 24 Oct 03 04:21:53 AM UTC 24 2469617133 ps
T33 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/3.spi_device_stress_all.3954382269 Oct 03 04:21:50 AM UTC 24 Oct 03 04:21:53 AM UTC 24 290582437 ps
T56 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_all.4023674945 Oct 03 04:21:31 AM UTC 24 Oct 03 04:21:54 AM UTC 24 2044270118 ps
T34 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/3.spi_device_sec_cm.1610491716 Oct 03 04:21:52 AM UTC 24 Oct 03 04:21:54 AM UTC 24 130736787 ps
T99 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/3.spi_device_alert_test.243883211 Oct 03 04:21:53 AM UTC 24 Oct 03 04:21:55 AM UTC 24 14864321 ps
T405 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/4.spi_device_csb_read.1350104733 Oct 03 04:21:54 AM UTC 24 Oct 03 04:21:56 AM UTC 24 25655062 ps
T406 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/4.spi_device_mem_parity.3081064562 Oct 03 04:21:54 AM UTC 24 Oct 03 04:21:56 AM UTC 24 27347406 ps
T46 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_and_tpm_min_idle.1041044360 Oct 03 04:21:27 AM UTC 24 Oct 03 04:21:58 AM UTC 24 1824045575 ps
T76 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_sts_read.4098892911 Oct 03 04:21:56 AM UTC 24 Oct 03 04:21:58 AM UTC 24 62251543 ps
T77 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/3.spi_device_intercept.17289891 Oct 03 04:21:47 AM UTC 24 Oct 03 04:21:59 AM UTC 24 1079717001 ps
T78 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_rw.1558124956 Oct 03 04:21:57 AM UTC 24 Oct 03 04:22:00 AM UTC 24 53544291 ps
T79 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/1.spi_device_mailbox.3402506797 Oct 03 04:21:30 AM UTC 24 Oct 03 04:22:01 AM UTC 24 18361282706 ps
T80 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/3.spi_device_read_buffer_direct.391417937 Oct 03 04:21:49 AM UTC 24 Oct 03 04:22:01 AM UTC 24 2017644440 ps
T47 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_all.3609522043 Oct 03 04:21:28 AM UTC 24 Oct 03 04:22:01 AM UTC 24 3858061351 ps
T81 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_read_hw_reg.2232172232 Oct 03 04:21:46 AM UTC 24 Oct 03 04:22:02 AM UTC 24 2430528682 ps
T70 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/3.spi_device_pass_addr_payload_swap.1986902725 Oct 03 04:21:47 AM UTC 24 Oct 03 04:22:05 AM UTC 24 3134542758 ps
T58 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_and_tpm.3443889807 Oct 03 04:21:31 AM UTC 24 Oct 03 04:22:07 AM UTC 24 15493160902 ps
T275 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/4.spi_device_upload.3409635124 Oct 03 04:22:01 AM UTC 24 Oct 03 04:22:07 AM UTC 24 353415181 ps
T168 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_mode.3411511689 Oct 03 04:22:02 AM UTC 24 Oct 03 04:22:08 AM UTC 24 490969862 ps
T206 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/3.spi_device_mailbox.3495403308 Oct 03 04:21:49 AM UTC 24 Oct 03 04:22:10 AM UTC 24 1753924899 ps
T35 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/4.spi_device_sec_cm.1776911398 Oct 03 04:22:09 AM UTC 24 Oct 03 04:22:12 AM UTC 24 700548080 ps
T110 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_read_hw_reg.1809326606 Oct 03 04:21:55 AM UTC 24 Oct 03 04:22:12 AM UTC 24 4003240894 ps
T124 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/4.spi_device_read_buffer_direct.822704743 Oct 03 04:22:03 AM UTC 24 Oct 03 04:22:12 AM UTC 24 844906707 ps
T283 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/0.spi_device_cfg_cmd.3800034091 Oct 03 04:21:26 AM UTC 24 Oct 03 04:22:12 AM UTC 24 6179522106 ps
T407 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/4.spi_device_alert_test.4115089479 Oct 03 04:22:10 AM UTC 24 Oct 03 04:22:12 AM UTC 24 46554074 ps
T53 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_all.135949879 Oct 03 04:21:41 AM UTC 24 Oct 03 04:22:14 AM UTC 24 5056643273 ps
T169 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_mode.4073435461 Oct 03 04:21:49 AM UTC 24 Oct 03 04:22:14 AM UTC 24 1555534391 ps
T408 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/5.spi_device_csb_read.3188156527 Oct 03 04:22:12 AM UTC 24 Oct 03 04:22:15 AM UTC 24 18399811 ps
T409 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/5.spi_device_mem_parity.880216417 Oct 03 04:22:13 AM UTC 24 Oct 03 04:22:15 AM UTC 24 49681809 ps
T113 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/4.spi_device_pass_addr_payload_swap.1769828514 Oct 03 04:21:59 AM UTC 24 Oct 03 04:22:16 AM UTC 24 7859642379 ps
T111 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/3.spi_device_cfg_cmd.1269348122 Oct 03 04:21:49 AM UTC 24 Oct 03 04:22:16 AM UTC 24 5356387601 ps
T109 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_all.532323225 Oct 03 04:21:46 AM UTC 24 Oct 03 04:22:16 AM UTC 24 1597826230 ps
T410 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_sts_read.3215501831 Oct 03 04:22:14 AM UTC 24 Oct 03 04:22:16 AM UTC 24 110050812 ps
T411 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_read_hw_reg.3132727536 Oct 03 04:22:13 AM UTC 24 Oct 03 04:22:19 AM UTC 24 2035476562 ps
T397 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_rw.2453098962 Oct 03 04:22:15 AM UTC 24 Oct 03 04:22:19 AM UTC 24 1607802597 ps
T66 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/3.spi_device_pass_cmd_filtering.2482727770 Oct 03 04:21:46 AM UTC 24 Oct 03 04:22:21 AM UTC 24 47913219357 ps
T95 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/5.spi_device_intercept.1353234242 Oct 03 04:22:16 AM UTC 24 Oct 03 04:22:23 AM UTC 24 418647260 ps
T208 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_mode.1590281776 Oct 03 04:22:17 AM UTC 24 Oct 03 04:22:23 AM UTC 24 124459983 ps
T96 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/4.spi_device_cfg_cmd.2749847338 Oct 03 04:22:02 AM UTC 24 Oct 03 04:22:26 AM UTC 24 7141568245 ps
T114 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/3.spi_device_upload.3849512796 Oct 03 04:21:49 AM UTC 24 Oct 03 04:22:26 AM UTC 24 44859254550 ps
T67 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/4.spi_device_pass_cmd_filtering.2535067785 Oct 03 04:21:57 AM UTC 24 Oct 03 04:22:27 AM UTC 24 4427085031 ps
T97 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/5.spi_device_cfg_cmd.2859978210 Oct 03 04:22:17 AM UTC 24 Oct 03 04:22:27 AM UTC 24 1189294774 ps
T412 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/5.spi_device_alert_test.3280741897 Oct 03 04:22:27 AM UTC 24 Oct 03 04:22:29 AM UTC 24 15205908 ps
T413 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/6.spi_device_csb_read.1543212602 Oct 03 04:22:28 AM UTC 24 Oct 03 04:22:30 AM UTC 24 135481304 ps
T170 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/5.spi_device_read_buffer_direct.3647342651 Oct 03 04:22:21 AM UTC 24 Oct 03 04:22:31 AM UTC 24 1020861112 ps
T414 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/6.spi_device_mem_parity.2672049768 Oct 03 04:22:28 AM UTC 24 Oct 03 04:22:31 AM UTC 24 55704992 ps
T415 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.3883921290 Oct 03 04:22:32 AM UTC 24 Oct 03 04:22:34 AM UTC 24 109200776 ps
T392 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_rw.2620579279 Oct 03 04:22:32 AM UTC 24 Oct 03 04:22:34 AM UTC 24 814019405 ps
T57 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_all.75814319 Oct 03 04:22:22 AM UTC 24 Oct 03 04:22:35 AM UTC 24 1662145201 ps
T416 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/6.spi_device_pass_cmd_filtering.3691883486 Oct 03 04:22:35 AM UTC 24 Oct 03 04:22:39 AM UTC 24 57680127 ps
T203 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/5.spi_device_upload.2406204835 Oct 03 04:22:17 AM UTC 24 Oct 03 04:22:40 AM UTC 24 9778147510 ps
T204 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/5.spi_device_pass_addr_payload_swap.2325593977 Oct 03 04:22:16 AM UTC 24 Oct 03 04:22:41 AM UTC 24 3587653802 ps
T417 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_read_hw_reg.3646064580 Oct 03 04:22:30 AM UTC 24 Oct 03 04:22:42 AM UTC 24 4287992760 ps
T82 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.354949614 Oct 03 04:21:41 AM UTC 24 Oct 03 04:22:42 AM UTC 24 7215494202 ps
T108 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_all.485673245 Oct 03 04:21:55 AM UTC 24 Oct 03 04:22:43 AM UTC 24 19066801522 ps
T201 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/6.spi_device_pass_addr_payload_swap.3768744324 Oct 03 04:22:35 AM UTC 24 Oct 03 04:22:44 AM UTC 24 5321954108 ps
T418 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/6.spi_device_cfg_cmd.690777752 Oct 03 04:22:40 AM UTC 24 Oct 03 04:22:46 AM UTC 24 431730380 ps
T243 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/5.spi_device_mailbox.778855503 Oct 03 04:22:17 AM UTC 24 Oct 03 04:22:47 AM UTC 24 1338573379 ps
T68 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/6.spi_device_upload.304129638 Oct 03 04:22:40 AM UTC 24 Oct 03 04:22:50 AM UTC 24 734245799 ps
T200 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/6.spi_device_mailbox.3330133286 Oct 03 04:22:39 AM UTC 24 Oct 03 04:22:51 AM UTC 24 941608471 ps
T419 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/6.spi_device_alert_test.4009301130 Oct 03 04:22:48 AM UTC 24 Oct 03 04:22:51 AM UTC 24 88877765 ps
T420 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/7.spi_device_csb_read.1964801610 Oct 03 04:22:49 AM UTC 24 Oct 03 04:22:51 AM UTC 24 28441845 ps
T245 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/6.spi_device_intercept.59154286 Oct 03 04:22:36 AM UTC 24 Oct 03 04:22:51 AM UTC 24 1272073848 ps
T421 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mem_parity.2036868031 Oct 03 04:22:51 AM UTC 24 Oct 03 04:22:53 AM UTC 24 108425998 ps
T422 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.3730973624 Oct 03 04:22:52 AM UTC 24 Oct 03 04:22:54 AM UTC 24 130498842 ps
T125 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/5.spi_device_pass_cmd_filtering.1232634515 Oct 03 04:22:15 AM UTC 24 Oct 03 04:22:55 AM UTC 24 5663033502 ps
T223 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_mode.3916525380 Oct 03 04:22:41 AM UTC 24 Oct 03 04:22:55 AM UTC 24 348463919 ps
T423 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_rw.277017187 Oct 03 04:22:53 AM UTC 24 Oct 03 04:22:55 AM UTC 24 33830338 ps
T424 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.3307494111 Oct 03 04:22:55 AM UTC 24 Oct 03 04:23:00 AM UTC 24 105854117 ps
T42 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_and_tpm.80625688 Oct 03 04:21:41 AM UTC 24 Oct 03 04:23:00 AM UTC 24 2156958207 ps
T425 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.1557839875 Oct 03 04:22:52 AM UTC 24 Oct 03 04:23:01 AM UTC 24 5050316873 ps
T287 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/7.spi_device_upload.1443485773 Oct 03 04:22:56 AM UTC 24 Oct 03 04:23:01 AM UTC 24 399119573 ps
T387 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_all.602779849 Oct 03 04:22:14 AM UTC 24 Oct 03 04:23:04 AM UTC 24 8050866639 ps
T285 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/7.spi_device_cfg_cmd.2572814853 Oct 03 04:23:01 AM UTC 24 Oct 03 04:23:05 AM UTC 24 227573624 ps
T207 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode.4153779700 Oct 03 04:23:02 AM UTC 24 Oct 03 04:23:12 AM UTC 24 781226249 ps
T205 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.3816837313 Oct 03 04:22:54 AM UTC 24 Oct 03 04:23:13 AM UTC 24 3482416650 ps
T267 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mailbox.2368183122 Oct 03 04:22:55 AM UTC 24 Oct 03 04:23:14 AM UTC 24 1823401807 ps
T379 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_all.4108480540 Oct 03 04:23:16 AM UTC 24 Oct 03 04:23:43 AM UTC 24 10441341753 ps
T202 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/7.spi_device_intercept.3053773092 Oct 03 04:22:55 AM UTC 24 Oct 03 04:23:15 AM UTC 24 2537358456 ps
T426 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/7.spi_device_alert_test.796870772 Oct 03 04:23:13 AM UTC 24 Oct 03 04:23:16 AM UTC 24 40719417 ps
T171 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/6.spi_device_read_buffer_direct.1026340283 Oct 03 04:22:43 AM UTC 24 Oct 03 04:23:16 AM UTC 24 9067776979 ps
T427 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/8.spi_device_csb_read.1024566208 Oct 03 04:23:15 AM UTC 24 Oct 03 04:23:17 AM UTC 24 75425783 ps
T428 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.2894517925 Oct 03 04:23:03 AM UTC 24 Oct 03 04:23:18 AM UTC 24 744817091 ps
T429 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_sts_read.2926834380 Oct 03 04:23:16 AM UTC 24 Oct 03 04:23:19 AM UTC 24 258000114 ps
T430 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mem_parity.441962579 Oct 03 04:23:16 AM UTC 24 Oct 03 04:23:19 AM UTC 24 52871215 ps
T296 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/4.spi_device_mailbox.168093206 Oct 03 04:22:00 AM UTC 24 Oct 03 04:23:22 AM UTC 24 7943834121 ps
T431 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/8.spi_device_intercept.2249813891 Oct 03 04:23:20 AM UTC 24 Oct 03 04:23:24 AM UTC 24 55645628 ps
T65 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.2880789516 Oct 03 04:23:20 AM UTC 24 Oct 03 04:23:25 AM UTC 24 116136036 ps
T432 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.3073821322 Oct 03 04:23:16 AM UTC 24 Oct 03 04:23:25 AM UTC 24 699868178 ps
T238 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.831997061 Oct 03 04:23:17 AM UTC 24 Oct 03 04:23:25 AM UTC 24 228885173 ps
T400 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_rw.2354350562 Oct 03 04:23:17 AM UTC 24 Oct 03 04:23:27 AM UTC 24 341469516 ps
T69 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_mode_ignore_cmds.3112809974 Oct 03 04:22:02 AM UTC 24 Oct 03 04:23:27 AM UTC 24 3745661958 ps
T383 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_all.2357607211 Oct 03 04:22:52 AM UTC 24 Oct 03 04:23:30 AM UTC 24 11930800213 ps
T284 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/8.spi_device_cfg_cmd.464046327 Oct 03 04:23:23 AM UTC 24 Oct 03 04:23:31 AM UTC 24 530043617 ps
T36 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/8.spi_device_stress_all.582974737 Oct 03 04:23:28 AM UTC 24 Oct 03 04:23:31 AM UTC 24 69236586 ps
T183 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode.3116322170 Oct 03 04:23:23 AM UTC 24 Oct 03 04:23:33 AM UTC 24 189016996 ps
T184 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/8.spi_device_alert_test.2582520505 Oct 03 04:23:31 AM UTC 24 Oct 03 04:23:33 AM UTC 24 17932462 ps
T185 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/9.spi_device_csb_read.3065207531 Oct 03 04:23:31 AM UTC 24 Oct 03 04:23:33 AM UTC 24 18265614 ps
T54 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_and_tpm_min_idle.2732963434 Oct 03 04:22:24 AM UTC 24 Oct 03 04:23:35 AM UTC 24 4542149111 ps
T186 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mem_parity.584145488 Oct 03 04:23:32 AM UTC 24 Oct 03 04:23:35 AM UTC 24 59292874 ps
T187 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_all.2827267521 Oct 03 04:22:31 AM UTC 24 Oct 03 04:23:35 AM UTC 24 14004772855 ps
T188 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.2439127482 Oct 03 04:23:34 AM UTC 24 Oct 03 04:23:36 AM UTC 24 28657770 ps
T189 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_all.200089418 Oct 03 04:23:34 AM UTC 24 Oct 03 04:23:36 AM UTC 24 42670667 ps
T190 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_rw.2481762605 Oct 03 04:23:35 AM UTC 24 Oct 03 04:23:38 AM UTC 24 16984930 ps
T286 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_all.562065254 Oct 03 04:22:43 AM UTC 24 Oct 03 04:23:38 AM UTC 24 21467445870 ps
T433 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.1453431263 Oct 03 04:23:26 AM UTC 24 Oct 03 04:23:39 AM UTC 24 1030117793 ps
T71 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.2632761979 Oct 03 04:23:36 AM UTC 24 Oct 03 04:23:40 AM UTC 24 177402365 ps
T293 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/9.spi_device_intercept.3062008270 Oct 03 04:23:37 AM UTC 24 Oct 03 04:23:43 AM UTC 24 98140318 ps
T317 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/9.spi_device_upload.4128337835 Oct 03 04:23:39 AM UTC 24 Oct 03 04:23:44 AM UTC 24 242202275 ps
T93 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_and_tpm_min_idle.927132743 Oct 03 04:21:50 AM UTC 24 Oct 03 04:23:45 AM UTC 24 41481367574 ps
T55 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_mode_ignore_cmds.619308093 Oct 03 04:22:20 AM UTC 24 Oct 03 04:23:46 AM UTC 24 16751130794 ps
T260 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mailbox.2505343669 Oct 03 04:23:20 AM UTC 24 Oct 03 04:23:47 AM UTC 24 14820378830 ps
T198 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/8.spi_device_upload.1745830451 Oct 03 04:23:21 AM UTC 24 Oct 03 04:23:47 AM UTC 24 91489348190 ps
T434 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/9.spi_device_alert_test.2984094824 Oct 03 04:23:47 AM UTC 24 Oct 03 04:23:49 AM UTC 24 18311382 ps
T435 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/10.spi_device_csb_read.1434435842 Oct 03 04:23:48 AM UTC 24 Oct 03 04:23:50 AM UTC 24 219395375 ps
T436 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/10.spi_device_mem_parity.1789724193 Oct 03 04:23:48 AM UTC 24 Oct 03 04:23:50 AM UTC 24 24943746 ps
T437 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.4100160913 Oct 03 04:23:34 AM UTC 24 Oct 03 04:23:51 AM UTC 24 939354302 ps
T249 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.1292445483 Oct 03 04:23:36 AM UTC 24 Oct 03 04:23:52 AM UTC 24 19348266225 ps
T438 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.752640380 Oct 03 04:23:43 AM UTC 24 Oct 03 04:23:53 AM UTC 24 3034293099 ps
T398 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_rw.2328939837 Oct 03 04:23:51 AM UTC 24 Oct 03 04:23:54 AM UTC 24 14219489 ps
T439 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_sts_read.475135886 Oct 03 04:23:51 AM UTC 24 Oct 03 04:23:54 AM UTC 24 115189180 ps
T306 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/9.spi_device_cfg_cmd.3952792396 Oct 03 04:23:39 AM UTC 24 Oct 03 04:23:56 AM UTC 24 1407301190 ps
T280 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode.3087519854 Oct 03 04:23:40 AM UTC 24 Oct 03 04:23:58 AM UTC 24 4339859461 ps
T338 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/10.spi_device_intercept.4197031785 Oct 03 04:23:55 AM UTC 24 Oct 03 04:24:01 AM UTC 24 190924991 ps
T101 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_all.3955667956 Oct 03 04:22:05 AM UTC 24 Oct 03 04:24:02 AM UTC 24 34241839519 ps
T440 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_read_hw_reg.3699672113 Oct 03 04:23:50 AM UTC 24 Oct 03 04:24:04 AM UTC 24 6720434262 ps
T244 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/10.spi_device_pass_addr_payload_swap.4076013075 Oct 03 04:23:53 AM UTC 24 Oct 03 04:24:05 AM UTC 24 323677658 ps
T102 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_mode_ignore_cmds.3689889511 Oct 03 04:21:49 AM UTC 24 Oct 03 04:24:05 AM UTC 24 72050787193 ps
T37 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/10.spi_device_stress_all.1983356809 Oct 03 04:24:06 AM UTC 24 Oct 03 04:24:08 AM UTC 24 34675127 ps
T441 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/10.spi_device_cfg_cmd.901948761 Oct 03 04:23:58 AM UTC 24 Oct 03 04:24:09 AM UTC 24 3653281731 ps
T442 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/10.spi_device_alert_test.3851645728 Oct 03 04:24:09 AM UTC 24 Oct 03 04:24:11 AM UTC 24 113185714 ps
T443 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/10.spi_device_read_buffer_direct.1898594286 Oct 03 04:24:02 AM UTC 24 Oct 03 04:24:11 AM UTC 24 236131192 ps
T444 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/11.spi_device_csb_read.480896645 Oct 03 04:24:10 AM UTC 24 Oct 03 04:24:12 AM UTC 24 15117743 ps
T381 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_all.3863752598 Oct 03 04:23:51 AM UTC 24 Oct 03 04:24:15 AM UTC 24 1343520519 ps
T445 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/11.spi_device_mem_parity.2755416700 Oct 03 04:24:12 AM UTC 24 Oct 03 04:24:15 AM UTC 24 65915342 ps
T300 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mailbox.1128469408 Oct 03 04:23:38 AM UTC 24 Oct 03 04:24:17 AM UTC 24 2562309097 ps
T446 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_sts_read.2346034155 Oct 03 04:24:15 AM UTC 24 Oct 03 04:24:18 AM UTC 24 72497040 ps
T399 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_rw.2681927106 Oct 03 04:24:16 AM UTC 24 Oct 03 04:24:19 AM UTC 24 76606206 ps
T38 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/0.spi_device_stress_all.1101706829 Oct 03 04:21:27 AM UTC 24 Oct 03 04:24:21 AM UTC 24 54104150694 ps
T447 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_mode.4178596866 Oct 03 04:23:59 AM UTC 24 Oct 03 04:24:21 AM UTC 24 578170483 ps
T241 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/10.spi_device_upload.1119408421 Oct 03 04:23:57 AM UTC 24 Oct 03 04:24:21 AM UTC 24 29374670991 ps
T276 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/10.spi_device_pass_cmd_filtering.3938544164 Oct 03 04:23:53 AM UTC 24 Oct 03 04:24:22 AM UTC 24 4296921994 ps
T330 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/11.spi_device_pass_cmd_filtering.3293696254 Oct 03 04:24:18 AM UTC 24 Oct 03 04:24:26 AM UTC 24 1241439937 ps
T294 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/11.spi_device_mailbox.1149900932 Oct 03 04:24:22 AM UTC 24 Oct 03 04:24:26 AM UTC 24 73742752 ps
T448 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_read_hw_reg.2330643106 Oct 03 04:24:12 AM UTC 24 Oct 03 04:24:28 AM UTC 24 2986046959 ps
T72 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_and_tpm.3921108501 Oct 03 04:23:44 AM UTC 24 Oct 03 04:24:31 AM UTC 24 10196362960 ps
T73 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/11.spi_device_pass_addr_payload_swap.2529095601 Oct 03 04:24:19 AM UTC 24 Oct 03 04:24:31 AM UTC 24 629634197 ps
T74 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_and_tpm_min_idle.3494221951 Oct 03 04:23:45 AM UTC 24 Oct 03 04:24:33 AM UTC 24 6764483560 ps
T39 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/11.spi_device_stress_all.118739196 Oct 03 04:24:33 AM UTC 24 Oct 03 04:24:36 AM UTC 24 59512567 ps
T449 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/11.spi_device_alert_test.3157542149 Oct 03 04:24:37 AM UTC 24 Oct 03 04:24:39 AM UTC 24 38054923 ps
T259 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/10.spi_device_mailbox.1205953639 Oct 03 04:23:55 AM UTC 24 Oct 03 04:24:40 AM UTC 24 4214475375 ps
T370 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_mode.924284456 Oct 03 04:24:23 AM UTC 24 Oct 03 04:24:42 AM UTC 24 599815081 ps
T450 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/12.spi_device_csb_read.1498934975 Oct 03 04:24:40 AM UTC 24 Oct 03 04:24:42 AM UTC 24 238563983 ps
T451 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/12.spi_device_mem_parity.145688040 Oct 03 04:24:41 AM UTC 24 Oct 03 04:24:44 AM UTC 24 30228525 ps
T452 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_sts_read.1822690522 Oct 03 04:24:43 AM UTC 24 Oct 03 04:24:46 AM UTC 24 68846376 ps
T453 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_rw.656277557 Oct 03 04:24:44 AM UTC 24 Oct 03 04:24:47 AM UTC 24 107185054 ps
T454 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/11.spi_device_read_buffer_direct.1815784135 Oct 03 04:24:27 AM UTC 24 Oct 03 04:24:49 AM UTC 24 23826017575 ps
T290 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/11.spi_device_intercept.1905926483 Oct 03 04:24:20 AM UTC 24 Oct 03 04:24:50 AM UTC 24 26990656865 ps
T382 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_all.902832156 Oct 03 04:24:13 AM UTC 24 Oct 03 04:24:52 AM UTC 24 8225791835 ps
T384 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_all.2247570934 Oct 03 04:24:43 AM UTC 24 Oct 03 04:24:54 AM UTC 24 2017819779 ps
T455 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/12.spi_device_intercept.2523495831 Oct 03 04:24:50 AM UTC 24 Oct 03 04:24:54 AM UTC 24 471675473 ps
T269 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/11.spi_device_upload.383254207 Oct 03 04:24:22 AM UTC 24 Oct 03 04:24:56 AM UTC 24 37500865827 ps
T239 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_and_tpm_min_idle.1310463581 Oct 03 04:21:31 AM UTC 24 Oct 03 04:24:57 AM UTC 24 301266038255 ps
T456 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/12.spi_device_upload.445435564 Oct 03 04:24:53 AM UTC 24 Oct 03 04:24:57 AM UTC 24 204613409 ps
T457 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/11.spi_device_cfg_cmd.528816110 Oct 03 04:24:22 AM UTC 24 Oct 03 04:24:59 AM UTC 24 5559045675 ps
T458 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_read_hw_reg.2120913578 Oct 03 04:24:42 AM UTC 24 Oct 03 04:25:01 AM UTC 24 27242032664 ps
T75 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode_ignore_cmds.826555247 Oct 03 04:23:03 AM UTC 24 Oct 03 04:25:01 AM UTC 24 16581366813 ps
T326 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/12.spi_device_pass_addr_payload_swap.4156948653 Oct 03 04:24:48 AM UTC 24 Oct 03 04:25:02 AM UTC 24 8835520424 ps
T197 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/12.spi_device_pass_cmd_filtering.1234551836 Oct 03 04:24:46 AM UTC 24 Oct 03 04:25:02 AM UTC 24 7510972266 ps
T459 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/12.spi_device_alert_test.1304187258 Oct 03 04:25:03 AM UTC 24 Oct 03 04:25:05 AM UTC 24 32024512 ps
T307 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/13.spi_device_pass_cmd_filtering.2622337312 Oct 03 04:25:09 AM UTC 24 Oct 03 04:25:15 AM UTC 24 368341908 ps
T460 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/13.spi_device_csb_read.805597342 Oct 03 04:25:03 AM UTC 24 Oct 03 04:25:05 AM UTC 24 20324456 ps
T178 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/5.spi_device_stress_all.1948888376 Oct 03 04:22:27 AM UTC 24 Oct 03 04:25:05 AM UTC 24 25016007810 ps
T461 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/12.spi_device_read_buffer_direct.1870785902 Oct 03 04:24:57 AM UTC 24 Oct 03 04:25:05 AM UTC 24 1084589335 ps
T462 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_sts_read.3537357449 Oct 03 04:25:06 AM UTC 24 Oct 03 04:25:08 AM UTC 24 77133163 ps
T463 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_rw.1666187069 Oct 03 04:25:06 AM UTC 24 Oct 03 04:25:08 AM UTC 24 109817480 ps
T464 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/13.spi_device_mem_parity.2816503375 Oct 03 04:25:06 AM UTC 24 Oct 03 04:25:08 AM UTC 24 25701992 ps
T316 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/12.spi_device_mailbox.2323131432 Oct 03 04:24:52 AM UTC 24 Oct 03 04:25:12 AM UTC 24 472731870 ps
T304 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/12.spi_device_cfg_cmd.3979096549 Oct 03 04:24:55 AM UTC 24 Oct 03 04:25:13 AM UTC 24 2773495704 ps
T465 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_read_hw_reg.887341210 Oct 03 04:25:06 AM UTC 24 Oct 03 04:25:14 AM UTC 24 668489641 ps
T466 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/13.spi_device_pass_addr_payload_swap.1129550502 Oct 03 04:25:09 AM UTC 24 Oct 03 04:25:15 AM UTC 24 164634550 ps
T309 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/13.spi_device_intercept.3310611468 Oct 03 04:25:09 AM UTC 24 Oct 03 04:25:16 AM UTC 24 77805758 ps
T331 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_mode_ignore_cmds.1882085182 Oct 03 04:24:26 AM UTC 24 Oct 03 04:25:17 AM UTC 24 18638284207 ps
T194 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/1.spi_device_stress_all.2111183060 Oct 03 04:21:31 AM UTC 24 Oct 03 04:25:18 AM UTC 24 98538796132 ps
T308 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/13.spi_device_cfg_cmd.4097170623 Oct 03 04:25:15 AM UTC 24 Oct 03 04:25:19 AM UTC 24 179266341 ps
T467 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_mode.1802439910 Oct 03 04:25:16 AM UTC 24 Oct 03 04:25:20 AM UTC 24 61711289 ps
T468 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/13.spi_device_alert_test.120423666 Oct 03 04:25:22 AM UTC 24 Oct 03 04:25:24 AM UTC 24 37226559 ps
T195 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_mode_ignore_cmds.115797617 Oct 03 04:21:39 AM UTC 24 Oct 03 04:25:25 AM UTC 24 137735426135 ps
T270 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/13.spi_device_upload.3792102118 Oct 03 04:25:13 AM UTC 24 Oct 03 04:25:25 AM UTC 24 1818499273 ps
T469 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/14.spi_device_csb_read.4102417295 Oct 03 04:25:25 AM UTC 24 Oct 03 04:25:27 AM UTC 24 18556684 ps
T470 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/14.spi_device_mem_parity.1882657569 Oct 03 04:25:26 AM UTC 24 Oct 03 04:25:28 AM UTC 24 362625986 ps
T393 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_all.1773075889 Oct 03 04:25:06 AM UTC 24 Oct 03 04:25:29 AM UTC 24 3006095246 ps
T471 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/13.spi_device_read_buffer_direct.284834090 Oct 03 04:25:17 AM UTC 24 Oct 03 04:25:29 AM UTC 24 758632645 ps
T386 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_and_tpm.3600077438 Oct 03 04:24:59 AM UTC 24 Oct 03 04:25:30 AM UTC 24 8477899695 ps
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T472 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_sts_read.282037658 Oct 03 04:25:29 AM UTC 24 Oct 03 04:25:31 AM UTC 24 117534067 ps
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T473 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_read_hw_reg.2827334341 Oct 03 04:25:26 AM UTC 24 Oct 03 04:25:32 AM UTC 24 3384127108 ps
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