Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	37893	1			T14	4		T18	2		T20	4
auto[SpiFlashAddrCfg]	7879	1			T6	2		T13	1		T14	4
auto[SpiFlashAddr3b]	9788	1			T18	6		T20	2		T24	6
auto[SpiFlashAddr4b]	8046	1			T14	2		T59	8		T62	4

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35284

1

T13

1

T14

10

T18

8

auto[1]

28322

1

T6

2

T20

6

T59

18

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33237

1

T6

2

T13

1

T14

2

auto[1]

30369

1

T14

8

T18

2

T20

4

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	42893	1			T6	2		T13	1		T14	4
values[1]	1175	1			T18	4		T59	6		T62	2
values[2]	1481	1			T59	8		T51	3		T56	1
values[3]	1482	1			T63	2		T94	2		T139	2
values[4]	1442	1			T63	2		T56	1		T46	2
values[5]	1586	1			T46	1		T77	2		T53	5
values[6]	1485	1			T14	2		T24	2		T41	3
values[7]	1520	1			T14	2		T18	2		T26	4
values[8]	10542	1			T14	2		T24	4		T59	2

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30020

1

T6

2

T14

10

T18

8

auto[1]

33586

1

T13

1

T51

3

T41

6

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

60095

1

T6

2

T13

1

T14

8

write

3511

1

T14

2

T62

2

T56

6

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

20361

1

T14

4

T18

2

T23

8

valids[0x1]

43245

1

T6

2

T13

1

T14

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1645	1			T18	2		T26	2		T64	2
internal_process_ops[0x5a]	1634	1			T60	6		T62	2		T56	2
internal_process_ops[0x05]	23067	1			T20	2		T21	2		T59	2
internal_process_ops[0x35]	1640	1			T14	2		T60	2		T63	4
internal_process_ops[0x15]	1663	1			T20	2		T21	2		T24	2
internal_process_ops[0x03]	1140	1			T6	2		T20	2		T46	2
internal_process_ops[0x0b]	1067	1			T18	4		T63	2		T94	2
internal_process_ops[0x3b]	1068	1			T41	3		T63	2		T139	2
internal_process_ops[0x6b]	1091	1			T26	4		T59	8		T41	2
internal_process_ops[0xbb]	1061	1			T24	4		T41	1		T94	2
internal_process_ops[0xeb]	1135	1			T13	1		T18	2		T51	3

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

61852

1

T6

2

T13

1

T14

10

auto[1]

1754

1

T56

5

T46

4

T70

2

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

61079

1

T6

2

T13

1

T14

10

auto[1]

2527

1

T46

4

T58

3

T53

6

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9397

1

T14

2

T18

2

T21

4

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6162

1

T20

4

T59

2

T46

4

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2113

1

T14

4

T62

2

T63

6

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1830

1

T6

2

T59

8

T46

9

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2528

1

T18

6

T24

6

T26

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2330

1

T20

2

T46

5

T70

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2191

1

T14

2

T62

4

T94

6

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1888

1

T59

8

T46

7

T70

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

106

1

T14

2

T62

2

T69

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

82

1

T54

2

T192

1

T193

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

84

1

T54

2

T72

1

T194

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

125

1

T46

1

T70

2

T69

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

127

1

T66

2

T69

1

T54

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

67

1

T195

1

T193

1

T196

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

77

1

T72

1

T74

1

T75

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

95

1

T69

2

T54

1

T55

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

122

1

T68

2

T69

3

T197

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

101

1

T69

1

T178

1

T194

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

92

1

T69

1

T54

1

T55

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

94

1

T55

2

T73

2

T74

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

97

1

T66

2

T69

3

T198

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

101

1

T46

3

T69

1

T72

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

100

1

T69

1

T54

1

T55

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

111

1

T69

1

T71

2

T55

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

12162

1

T56

4

T58

16

T53

72

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

9311

1

T56

3

T53

51

T57

23

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1505

1

T13

1

T41

3

T56

1

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1577

1

T53

11

T57

2

T82

5

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2037

1

T51

3

T41

3

T56

4

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1969

1

T58

5

T53

12

T57

5

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1509

1

T58

1

T53

5

T57

5

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1586

1

T56

2

T53

13

T57

8

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

97

1

T93

1

T101

1

T102

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

153

1

T56

2

T53

1

T101

5

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

114

1

T58

2

T93

3

T38

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

100

1

T53

4

T42

1

T93

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

129

1

T58

1

T53

1

T102

4

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

118

1

T57

2

T102

3

T38

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

125

1

T53

1

T42

4

T93

4

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

116

1

T82

1

T42

5

T101

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

139

1

T53

2

T102

1

T178

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

156

1

T58

5

T82

1

T101

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

110

1

T101

2

T102

1

T199

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

110

1

T93

1

T102

2

T38

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

114

1

T56

1

T57

1

T82

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

133

1

T56

3

T93

2

T102

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

124

1

T82

3

T93

1

T102

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

92

1

T82

1

T42

1

T93

3

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4121	1			T23	8		T61	8		T46	5
auto[0]	values[0]	valids[0x1]	14389	1			T6	2		T14	4		T18	2
auto[0]	values[1]	valids[0x1]	594	1			T18	4		T59	6		T62	2
auto[0]	values[2]	valids[0x0]	517	1			T59	8		T46	2		T113	6
auto[0]	values[2]	valids[0x1]	281	1			T46	1		T200	2		T69	4
auto[0]	values[3]	valids[0x0]	539	1			T63	2		T94	2		T139	2
auto[0]	values[3]	valids[0x1]	290	1			T67	2		T201	2		T202	4
auto[0]	values[4]	valids[0x0]	577	1			T63	2		T46	1		T77	2
auto[0]	values[4]	valids[0x1]	267	1			T46	1		T114	2		T203	2
auto[0]	values[5]	valids[0x0]	600	1			T46	1		T77	2		T204	2
auto[0]	values[5]	valids[0x1]	287	1			T205	2		T69	2		T54	1
auto[0]	values[6]	valids[0x0]	516	1			T14	2		T24	2		T62	2
auto[0]	values[6]	valids[0x1]	321	1			T46	2		T206	4		T69	7
auto[0]	values[7]	valids[0x0]	517	1			T14	2		T18	2		T26	4
auto[0]	values[7]	valids[0x1]	319	1			T64	2		T63	2		T69	3
auto[0]	values[8]	valids[0x0]	3655	1			T24	4		T64	2		T62	4
auto[0]	values[8]	valids[0x1]	2230	1			T14	2		T59	2		T46	4
auto[1]	values[0]	valids[0x0]	4181	1			T56	2		T58	3		T53	28
auto[1]	values[0]	valids[0x1]	20202	1			T13	1		T56	12		T58	19
auto[1]	values[1]	valids[0x1]	581	1			T53	2		T82	4		T42	2
auto[1]	values[2]	valids[0x0]	429	1			T51	3		T56	1		T58	3
auto[1]	values[2]	valids[0x1]	254	1			T58	3		T57	2		T82	1
auto[1]	values[3]	valids[0x0]	386	1			T53	5		T42	1		T207	1
auto[1]	values[3]	valids[0x1]	267	1			T57	1		T82	1		T42	2
auto[1]	values[4]	valids[0x0]	362	1			T56	1		T53	2		T42	8
auto[1]	values[4]	valids[0x1]	236	1			T53	1		T208	1		T82	2
auto[1]	values[5]	valids[0x0]	419	1			T53	2		T42	7		T93	3
auto[1]	values[5]	valids[0x1]	280	1			T53	3		T82	1		T42	2
auto[1]	values[6]	valids[0x0]	368	1			T41	3		T58	1		T53	2
auto[1]	values[6]	valids[0x1]	280	1			T56	1		T57	3		T82	3
auto[1]	values[7]	valids[0x0]	418	1			T58	1		T53	2		T57	2
auto[1]	values[7]	valids[0x1]	266	1			T53	2		T42	1		T93	1
auto[1]	values[8]	valids[0x0]	2756	1			T41	3		T56	1		T168	2
auto[1]	values[8]	valids[0x1]	1901	1			T56	2		T168	3		T53	16