Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3321910

1

T6

1

T7

1

T13

3

auto[1]

35745

1

T46

9

T58

10

T53

85

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

819881

1

T6

1

T7

1

T13

3

auto[1]

2537774

1

T21

1352

T24

5528

T26

3894

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	676543	1			T6	1		T7	1		T13	3
auto[524288:1048575]	448269	1			T23	23		T61	2		T60	293
auto[1048576:1572863]	330026	1			T18	267		T21	108		T23	195
auto[1572864:2097151]	358028	1			T18	4		T21	501		T23	164
auto[2097152:2621439]	428389	1			T21	585		T23	10		T77	950
auto[2621440:3145727]	314540	1			T18	424		T23	31		T60	2
auto[3145728:3670015]	391137	1			T18	203		T21	85		T23	9
auto[3670016:4194303]	410723	1			T18	827		T21	5		T23	6

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2572723

1

T6

1

T7

1

T13

3

auto[1]

784932

1

T18

2086

T21

663

T23

321

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2868890

1

T6

1

T7

1

T13

3

auto[1]

488765

1

T61

6

T56

1

T46

5

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	174945	1			T6	1		T7	1		T13	3
auto[0]	auto[0]	auto[0:524287]	auto[1]	434457	1			T21	643		T24	5528		T26	3894
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	117639	1			T23	23		T60	293		T63	10
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	260959	1			T53	512		T57	2511		T243	153
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	79508	1			T18	267		T21	71		T23	195
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	201566	1			T21	37		T60	250		T63	69
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	84026	1			T18	4		T21	248		T23	164
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	219534	1			T21	253		T82	256		T243	2217
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	111511	1			T21	170		T23	10		T77	950
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	247997	1			T21	415		T53	257		T57	4
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	50009	1			T18	424		T23	31		T60	2
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	204524	1			T56	256		T53	256		T82	867
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	87532	1			T18	203		T21	81		T23	9
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	228311	1			T21	4		T60	254		T56	4
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	93826	1			T18	827		T21	5		T23	6
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	243183	1			T60	2220		T63	12		T46	513
auto[0]	auto[1]	auto[0:524287]	auto[0]	1127	1			T61	4		T46	1		T58	1
auto[0]	auto[1]	auto[0:524287]	auto[1]	59514	1			T42	257		T93	512		T102	327
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	1025	1			T61	2		T283	3		T82	1
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	60280	1			T82	256		T42	256		T54	3234
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	787	1			T82	2		T69	8		T284	5
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	44228	1			T82	1726		T102	567		T38	2634
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	1500	1			T58	4		T283	814		T69	2
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	50075	1			T58	1		T93	4		T38	256
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	2417	1			T283	388		T53	1		T82	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	63193	1			T53	512		T42	1		T69	2
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	1722	1			T46	1		T283	813		T53	3
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	54466	1			T46	3		T53	1		T82	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	5742	1			T56	1		T283	4011		T42	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	65635	1			T42	915		T54	1		T102	128
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	2252	1			T58	2		T53	1		T285	4
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	68420	1			T58	1		T53	1		T286	4037
auto[1]	auto[0]	auto[0:524287]	auto[0]	650	1			T46	2		T58	1		T53	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	4931	1			T46	3		T58	4		T53	14
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	500	1			T57	1		T69	27		T54	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	6713	1			T57	5		T54	24		T55	496
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	384	1			T82	1		T42	1		T93	3
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2301	1			T82	1		T42	15		T93	29
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	359	1			T42	6		T69	23		T54	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1954	1			T42	53		T69	141		T54	39
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	411	1			T53	1		T57	1		T42	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2382	1			T53	2		T57	18		T42	5
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	428	1			T42	1		T55	7		T101	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2714	1			T42	1		T101	8		T102	130
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	394	1			T46	1		T53	1		T42	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2850	1			T46	1		T53	22		T42	2
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	433	1			T46	1		T42	1		T69	17
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1959	1			T46	1		T55	127		T101	27
auto[1]	auto[1]	auto[0:524287]	auto[0]	104	1			T42	1		T102	18		T38	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	815	1			T42	10		T38	2		T231	95
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	117	1			T93	1		T102	5		T199	2
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	1036	1			T93	2		T102	256		T199	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	88	1			T69	7		T102	16		T38	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	1164	1			T102	77		T38	1		T178	5
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	91	1			T58	1		T93	2		T75	4
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	489	1			T58	1		T93	8		T75	128
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	62	1			T42	1		T69	5		T93	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	416	1			T93	4		T193	4		T257	3
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	96	1			T53	1		T82	1		T42	2
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	581	1			T53	30		T82	12		T42	8
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	98	1			T54	1		T102	3		T199	3
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	575	1			T54	12		T199	2		T193	3
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	98	1			T58	1		T53	1		T230	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	552	1			T58	2		T53	11		T230	20

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2066290	1			T6	1		T7	1		T13	3
auto[0]	auto[0]	auto[1]	773237	1			T18	2086		T21	663		T23	321
auto[0]	auto[1]	auto[0]	471424	1			T61	6		T56	1		T46	5
auto[0]	auto[1]	auto[1]	10959	1			T283	6019		T53	2		T42	1
auto[1]	auto[0]	auto[0]	28759	1			T46	9		T58	5		T53	41
auto[1]	auto[0]	auto[1]	604	1			T53	1		T69	10		T55	8
auto[1]	auto[1]	auto[0]	6250	1			T58	5		T53	42		T82	13
auto[1]	auto[1]	auto[1]	132	1			T53	1		T69	1		T102	7