Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2725191	1			T1	1		T2	1		T3	1
all_pins[1]	2725191	1			T1	1		T2	1		T3	1
all_pins[2]	2725191	1			T1	1		T2	1		T3	1
all_pins[3]	2725191	1			T1	1		T2	1		T3	1
all_pins[4]	2725191	1			T1	1		T2	1		T3	1
all_pins[5]	2725191	1			T1	1		T2	1		T3	1
all_pins[6]	2725191	1			T1	1		T2	1		T3	1
all_pins[7]	2725191	1			T1	1		T2	1		T3	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	21788684	1			T1	8		T2	8		T3	8
values[0x1]	12844	1			T33	5		T36	21		T37	18
transitions[0x0=>0x1]	12079	1			T33	4		T36	17		T37	11
transitions[0x1=>0x0]	12092	1			T33	4		T36	17		T37	11

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2724474	1			T1	1		T2	1		T3	1
all_pins[0]	values[0x1]	717	1			T36	2		T37	2		T38	3
all_pins[0]	transitions[0x0=>0x1]	328	1			T37	1		T38	1		T39	2
all_pins[0]	transitions[0x1=>0x0]	332	1			T33	1		T36	2		T37	3
all_pins[1]	values[0x0]	2724470	1			T1	1		T2	1		T3	1
all_pins[1]	values[0x1]	721	1			T33	1		T36	4		T37	4
all_pins[1]	transitions[0x0=>0x1]	631	1			T33	1		T36	3		T37	4
all_pins[1]	transitions[0x1=>0x0]	134	1			T36	4		T37	1		T38	1
all_pins[2]	values[0x0]	2724967	1			T1	1		T2	1		T3	1
all_pins[2]	values[0x1]	224	1			T36	5		T37	1		T38	1
all_pins[2]	transitions[0x0=>0x1]	188	1			T36	5		T38	1		T39	8
all_pins[2]	transitions[0x1=>0x0]	161	1			T36	2		T37	2		T38	4
all_pins[3]	values[0x0]	2724994	1			T1	1		T2	1		T3	1
all_pins[3]	values[0x1]	197	1			T36	2		T37	3		T38	4
all_pins[3]	transitions[0x0=>0x1]	149	1			T36	1		T37	2		T38	4
all_pins[3]	transitions[0x1=>0x0]	131	1			T37	1		T39	4		T178	2
all_pins[4]	values[0x0]	2725012	1			T1	1		T2	1		T3	1
all_pins[4]	values[0x1]	179	1			T36	1		T37	2		T39	4
all_pins[4]	transitions[0x0=>0x1]	130	1			T36	1		T37	1		T39	1
all_pins[4]	transitions[0x1=>0x0]	1427	1			T33	2		T36	3		T37	1
all_pins[5]	values[0x0]	2723715	1			T1	1		T2	1		T3	1
all_pins[5]	values[0x1]	1476	1			T33	2		T36	3		T37	2
all_pins[5]	transitions[0x0=>0x1]	1429	1			T33	1		T36	3		T37	1
all_pins[5]	transitions[0x1=>0x0]	9083	1			T37	2		T38	5		T39	5
all_pins[6]	values[0x0]	2716061	1			T1	1		T2	1		T3	1
all_pins[6]	values[0x1]	9130	1			T33	1		T37	3		T38	5
all_pins[6]	transitions[0x0=>0x1]	9084	1			T33	1		T37	2		T38	4
all_pins[6]	transitions[0x1=>0x0]	154	1			T33	1		T36	4		T39	4
all_pins[7]	values[0x0]	2724991	1			T1	1		T2	1		T3	1
all_pins[7]	values[0x1]	200	1			T33	1		T36	4		T37	1
all_pins[7]	transitions[0x0=>0x1]	140	1			T33	1		T36	4		T38	1
all_pins[7]	transitions[0x1=>0x0]	670	1			T36	2		T37	1		T38	3