Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17032

1

T14

10

T18

8

T21

4

auto[1]

12988

1

T6

2

T20

6

T59

18

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3707	1			T24	8		T62	12		T243	18
values[1]	3619	1			T21	4		T60	10		T64	6
values[2]	3730	1			T6	2		T14	10		T59	18
values[3]	4071	1			T20	6		T113	16		T202	16
values[4]	3616	1			T23	8		T26	8		T79	2
values[5]	3683	1			T61	8		T63	12		T46	22
values[6]	4009	1			T18	8		T94	8		T66	18
values[7]	3585	1			T139	8		T46	27		T283	8

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4146	1			T23	8		T61	8		T46	27
values[1]	3064	1			T94	8		T283	8		T67	10
values[2]	3826	1			T6	2		T20	6		T26	8
values[3]	3420	1			T24	8		T64	6		T62	12
values[4]	4115	1			T21	4		T59	18		T63	12
values[5]	4155	1			T18	8		T79	2		T287	2
values[6]	3854	1			T14	10		T77	10		T66	18
values[7]	3440	1			T60	10		T139	8		T206	16

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	253	1			T68	8		T288	4		T289	12
auto[0]	values[0]	values[1]	244	1			T284	16		T55	11		T260	6
auto[0]	values[0]	values[2]	329	1			T290	12		T178	11		T196	10
auto[0]	values[0]	values[3]	353	1			T24	8		T62	12		T74	12
auto[0]	values[0]	values[4]	388	1			T153	16		T291	10		T292	11
auto[0]	values[0]	values[5]	199	1			T75	7		T246	5		T179	15
auto[0]	values[0]	values[6]	250	1			T293	4		T294	2		T74	64
auto[0]	values[0]	values[7]	206	1			T243	18		T55	13		T72	21
auto[0]	values[1]	values[0]	313	1			T72	14		T75	13		T192	8
auto[0]	values[1]	values[1]	277	1			T125	16		T69	14		T55	11
auto[0]	values[1]	values[2]	312	1			T275	4		T203	16		T286	15
auto[0]	values[1]	values[3]	228	1			T64	6		T111	6		T55	25
auto[0]	values[1]	values[4]	242	1			T21	4		T229	11		T246	68
auto[0]	values[1]	values[5]	254	1			T75	11		T295	12		T247	8
auto[0]	values[1]	values[6]	410	1			T77	10		T296	6		T69	14
auto[0]	values[1]	values[7]	143	1			T60	10		T75	7		T194	10
auto[0]	values[2]	values[0]	237	1			T96	4		T54	12		T156	9
auto[0]	values[2]	values[1]	288	1			T75	30		T156	89		T227	8
auto[0]	values[2]	values[2]	342	1			T238	22		T69	13		T54	6
auto[0]	values[2]	values[3]	256	1			T229	11		T242	13		T297	8
auto[0]	values[2]	values[4]	324	1			T298	10		T299	15		T219	16
auto[0]	values[2]	values[5]	325	1			T287	2		T197	18		T270	16
auto[0]	values[2]	values[6]	187	1			T14	10		T178	10		T181	10
auto[0]	values[2]	values[7]	265	1			T114	22		T54	9		T300	6
auto[0]	values[3]	values[0]	317	1			T54	15		T195	21		T261	12
auto[0]	values[3]	values[1]	289	1			T202	16		T178	13		T194	8
auto[0]	values[3]	values[2]	233	1			T69	8		T75	16		T156	9
auto[0]	values[3]	values[3]	197	1			T249	16		T153	12		T219	14
auto[0]	values[3]	values[4]	244	1			T272	10		T268	14		T301	21
auto[0]	values[3]	values[5]	249	1			T69	9		T196	27		T302	2
auto[0]	values[3]	values[6]	293	1			T69	10		T194	14		T195	26
auto[0]	values[3]	values[7]	253	1			T75	13		T178	10		T303	2
auto[0]	values[4]	values[0]	339	1			T23	8		T69	10		T195	9
auto[0]	values[4]	values[1]	177	1			T67	10		T304	10		T305	2
auto[0]	values[4]	values[2]	301	1			T26	8		T54	36		T178	14
auto[0]	values[4]	values[3]	161	1			T229	11		T219	9		T246	24
auto[0]	values[4]	values[4]	250	1			T276	6		T259	6		T193	11
auto[0]	values[4]	values[5]	253	1			T79	2		T195	10		T229	10
auto[0]	values[4]	values[6]	219	1			T97	12		T274	8		T193	12
auto[0]	values[4]	values[7]	144	1			T206	16		T195	14		T193	7
auto[0]	values[5]	values[0]	393	1			T61	8		T156	13		T232	12
auto[0]	values[5]	values[1]	148	1			T69	17		T193	11		T163	19
auto[0]	values[5]	values[2]	109	1			T46	11		T285	8		T306	10
auto[0]	values[5]	values[3]	224	1			T69	13		T193	28		T232	21
auto[0]	values[5]	values[4]	269	1			T63	12		T55	21		T307	2
auto[0]	values[5]	values[5]	255	1			T308	22		T192	8		T218	8
auto[0]	values[5]	values[6]	430	1			T205	6		T309	4		T193	9
auto[0]	values[5]	values[7]	367	1			T195	15		T268	12		T232	12
auto[0]	values[6]	values[0]	178	1			T75	14		T193	6		T310	8
auto[0]	values[6]	values[1]	251	1			T94	8		T279	10		T292	9
auto[0]	values[6]	values[2]	201	1			T69	9		T74	9		T178	8
auto[0]	values[6]	values[3]	351	1			T250	12		T311	8		T312	8
auto[0]	values[6]	values[4]	353	1			T241	20		T75	13		T229	9
auto[0]	values[6]	values[5]	421	1			T18	8		T75	7		T266	2
auto[0]	values[6]	values[6]	287	1			T66	18		T69	5		T75	10
auto[0]	values[6]	values[7]	279	1			T196	6		T313	6		T219	18
auto[0]	values[7]	values[0]	449	1			T46	12		T229	18		T193	14
auto[0]	values[7]	values[1]	170	1			T283	8		T55	11		T72	18
auto[0]	values[7]	values[2]	304	1			T75	12		T178	15		T314	4
auto[0]	values[7]	values[3]	206	1			T95	8		T245	12		T267	4
auto[0]	values[7]	values[4]	267	1			T269	18		T193	13		T315	28
auto[0]	values[7]	values[5]	316	1			T55	21		T74	44		T316	12
auto[0]	values[7]	values[6]	117	1			T200	8		T317	6		T192	16
auto[0]	values[7]	values[7]	143	1			T139	8		T318	9		T219	13
auto[1]	values[0]	values[0]	137	1			T319	12		T310	5		T225	8
auto[1]	values[0]	values[1]	231	1			T55	9		T193	6		T219	11
auto[1]	values[0]	values[2]	117	1			T178	9		T196	10		T232	6
auto[1]	values[0]	values[3]	232	1			T74	27		T318	13		T219	11
auto[1]	values[0]	values[4]	173	1			T153	11		T292	9		T163	15
auto[1]	values[0]	values[5]	112	1			T75	13		T246	15		T179	5
auto[1]	values[0]	values[6]	306	1			T74	7		T163	7		T278	10
auto[1]	values[0]	values[7]	177	1			T55	7		T72	11		T292	7
auto[1]	values[1]	values[0]	242	1			T70	6		T244	14		T72	6
auto[1]	values[1]	values[1]	126	1			T201	6		T69	6		T55	9
auto[1]	values[1]	values[2]	173	1			T286	5		T246	5		T310	8
auto[1]	values[1]	values[3]	247	1			T65	2		T71	6		T55	15
auto[1]	values[1]	values[4]	264	1			T229	9		T246	12		T310	25
auto[1]	values[1]	values[5]	118	1			T75	9		T247	12		T179	8
auto[1]	values[1]	values[6]	170	1			T69	6		T229	8		T261	5
auto[1]	values[1]	values[7]	100	1			T75	13		T194	13		T310	20
auto[1]	values[2]	values[0]	228	1			T54	8		T156	39		T163	12
auto[1]	values[2]	values[1]	131	1			T75	10		T156	12		T219	9
auto[1]	values[2]	values[2]	221	1			T6	2		T69	7		T54	64
auto[1]	values[2]	values[3]	152	1			T229	9		T242	8		T182	13
auto[1]	values[2]	values[4]	179	1			T59	18		T299	7		T219	4
auto[1]	values[2]	values[5]	202	1			T196	13		T255	9		T320	11
auto[1]	values[2]	values[6]	150	1			T178	12		T181	10		T321	7
auto[1]	values[2]	values[7]	243	1			T54	11		T246	9		T310	3
auto[1]	values[3]	values[0]	164	1			T54	5		T195	19		T322	18
auto[1]	values[3]	values[1]	125	1			T178	7		T194	12		T261	5
auto[1]	values[3]	values[2]	311	1			T20	6		T113	16		T69	12
auto[1]	values[3]	values[3]	211	1			T323	2		T153	8		T219	6
auto[1]	values[3]	values[4]	240	1			T268	6		T310	27		T236	53
auto[1]	values[3]	values[5]	491	1			T69	11		T196	4		T318	162
auto[1]	values[3]	values[6]	180	1			T69	10		T194	7		T195	14
auto[1]	values[3]	values[7]	274	1			T75	7		T178	10		T247	11
auto[1]	values[4]	values[0]	134	1			T69	10		T195	11		T156	7
auto[1]	values[4]	values[1]	122	1			T153	6		T255	46		T324	9
auto[1]	values[4]	values[2]	443	1			T54	164		T178	6		T219	7
auto[1]	values[4]	values[3]	130	1			T229	9		T219	11		T246	7
auto[1]	values[4]	values[4]	190	1			T193	54		T156	5		T225	6
auto[1]	values[4]	values[5]	348	1			T195	10		T229	10		T193	17
auto[1]	values[4]	values[6]	201	1			T193	25		T325	14		T219	10
auto[1]	values[4]	values[7]	204	1			T195	6		T193	25		T196	8
auto[1]	values[5]	values[0]	224	1			T156	67		T232	8		T310	8
auto[1]	values[5]	values[1]	137	1			T69	3		T326	20		T193	31
auto[1]	values[5]	values[2]	107	1			T46	11		T232	54		T310	9
auto[1]	values[5]	values[3]	145	1			T69	7		T193	12		T232	8
auto[1]	values[5]	values[4]	230	1			T55	19		T327	6		T328	6
auto[1]	values[5]	values[5]	191	1			T192	12		T196	8		T318	14
auto[1]	values[5]	values[6]	240	1			T193	26		T277	9		T163	23
auto[1]	values[5]	values[7]	214	1			T195	5		T268	8		T232	8
auto[1]	values[6]	values[0]	225	1			T75	6		T193	25		T310	35
auto[1]	values[6]	values[1]	187	1			T292	11		T247	11		T225	35
auto[1]	values[6]	values[2]	134	1			T69	11		T74	42		T178	12
auto[1]	values[6]	values[3]	167	1			T246	13		T163	22		T179	10
auto[1]	values[6]	values[4]	296	1			T75	7		T229	11		T193	10
auto[1]	values[6]	values[5]	209	1			T73	14		T75	13		T229	12
auto[1]	values[6]	values[6]	199	1			T69	15		T75	10		T156	10
auto[1]	values[6]	values[7]	271	1			T204	18		T196	14		T219	2
auto[1]	values[7]	values[0]	313	1			T46	15		T229	2		T193	10
auto[1]	values[7]	values[1]	161	1			T55	9		T72	9		T178	7
auto[1]	values[7]	values[2]	189	1			T75	8		T178	14		T229	8
auto[1]	values[7]	values[3]	160	1			T163	10		T310	11		T182	9
auto[1]	values[7]	values[4]	206	1			T193	10		T329	2		T225	46
auto[1]	values[7]	values[5]	212	1			T55	19		T74	6		T318	7
auto[1]	values[7]	values[6]	215	1			T192	6		T232	149		T321	9
auto[1]	values[7]	values[7]	157	1			T318	11		T219	7		T292	60