Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	469	1			T18	6		T63	6		T94	2
auto[ReadAddrCrossIntoMailbox]	329	1			T94	2		T206	4		T267	2
auto[ReadAddrCrossOutOfMailbox]	392	1			T94	2		T69	1		T54	2
auto[ReadAddrCrossAllMailbox]	240	1			T206	4		T200	2		T267	2
auto[ReadAddrOutsideMailbox]	3541	1			T6	2		T20	2		T24	4

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2437

1

T6

1

T18

3

T20

1

auto[1]

2534

1

T6

1

T18

3

T20

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	842	1			T6	2		T20	2		T46	2
read_ops[0x0b]	823	1			T18	4		T63	2		T94	2
read_ops[0x3b]	833	1			T63	2		T139	2		T77	2
read_ops[0x6b]	830	1			T26	4		T59	8		T62	4
read_ops[0xbb]	806	1			T24	4		T94	2		T46	2
read_ops[0xeb]	837	1			T18	2		T62	2		T63	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	51	1			T260	1		T259	1		T290	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	46	1			T260	1		T74	1		T259	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T196	3		T318	1		T292	3
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T229	1		T193	1		T232	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	40	1			T72	1		T178	1		T194	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	36	1			T54	1		T178	1		T193	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	22	1			T260	1		T331	1		T268	2
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	24	1			T260	1		T75	1		T310	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	307	1			T6	1		T20	1		T77	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	265	1			T6	1		T20	1		T46	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	37	1			T18	2		T63	1		T75	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	39	1			T18	2		T63	1		T55	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	34	1			T54	2		T316	1		T196	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T72	1		T178	1		T316	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	42	1			T75	1		T316	1		T229	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	35	1			T55	1		T72	1		T316	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T54	1		T316	1		T219	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T69	1		T55	1		T72	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	277	1			T94	1		T46	1		T204	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	297	1			T94	1		T46	2		T204	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	37	1			T63	1		T69	1		T290	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	46	1			T63	1		T69	3		T290	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T267	1		T72	1		T318	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T267	1		T55	1		T229	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T294	1		T178	1		T193	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	34	1			T69	1		T294	1		T229	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T267	1		T69	1		T268	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	23	1			T267	1		T246	1		T255	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	305	1			T139	1		T77	1		T113	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	294	1			T139	1		T77	1		T113	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	29	1			T77	1		T178	1		T289	3
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	30	1			T77	1		T55	1		T72	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T206	1		T178	1		T156	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	32	1			T206	1		T69	1		T74	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	32	1			T55	1		T75	1		T159	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	30	1			T55	2		T331	1		T195	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T206	1		T178	1		T310	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T206	1		T54	1		T75	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	279	1			T26	2		T59	4		T62	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	336	1			T26	2		T59	4		T62	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T94	1		T77	1		T74	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	46	1			T94	1		T77	1		T69	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T54	1		T178	2		T153	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	29	1			T54	1		T55	1		T156	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T259	1		T178	1		T268	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T54	1		T259	1		T178	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	11	1			T178	1		T246	1		T310	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T229	1		T261	2		T310	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	287	1			T24	2		T46	1		T275	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	302	1			T24	2		T46	1		T275	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T18	1		T63	1		T300	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	43	1			T18	1		T63	1		T300	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	29	1			T94	1		T206	1		T300	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	33	1			T94	1		T206	1		T54	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	31	1			T94	1		T75	1		T159	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	32	1			T94	1		T75	1		T178	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	24	1			T206	1		T200	1		T75	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T206	1		T200	1		T69	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	292	1			T62	1		T77	1		T95	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	300	1			T62	1		T46	4		T77	1