Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4309	1			T46	22		T206	16		T97	12
values[1]	4080	1			T20	6		T79	2		T283	8
values[2]	3618	1			T46	27		T95	8		T67	10
values[3]	3700	1			T21	4		T24	8		T61	8
values[4]	3864	1			T6	2		T14	10		T18	8
values[5]	3792	1			T275	4		T111	6		T114	22
values[6]	3797	1			T23	8		T60	10		T59	18
values[7]	2860	1			T63	12		T94	8		T139	8

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3950	1			T64	6		T46	49		T114	22
values[1]	3920	1			T14	10		T24	8		T26	8
values[2]	3357	1			T21	4		T23	8		T59	18
values[3]	3724	1			T61	8		T139	8		T79	2
values[4]	3612	1			T20	6		T62	12		T94	8
values[5]	3834	1			T18	8		T206	16		T95	8
values[6]	3730	1			T6	2		T111	6		T66	18
values[7]	3893	1			T60	10		T63	12		T70	6

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29244

1

T6

2

T14

10

T18

8

auto[1]

776

1

T46

4

T70

2

T69

7

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	568	1			T46	21		T69	19		T54	166
auto[0]	values[0]	values[1]	494	1			T97	12		T241	20		T72	31
auto[0]	values[0]	values[2]	291	1			T296	6		T218	8		T196	18
auto[0]	values[0]	values[3]	445	1			T69	18		T229	20		T163	26
auto[0]	values[0]	values[4]	845	1			T69	20		T72	26		T332	16
auto[0]	values[0]	values[5]	365	1			T206	16		T54	20		T308	22
auto[0]	values[0]	values[6]	645	1			T75	20		T195	18		T229	18
auto[0]	values[0]	values[7]	541	1			T288	4		T268	20		T319	20
auto[0]	values[1]	values[0]	649	1			T193	20		T156	78		T196	48
auto[0]	values[1]	values[1]	535	1			T54	33		T55	20		T331	18
auto[0]	values[1]	values[2]	272	1			T202	16		T333	8		T164	49
auto[0]	values[1]	values[3]	469	1			T79	2		T283	8		T65	2
auto[0]	values[1]	values[4]	504	1			T20	6		T178	20		T153	42
auto[0]	values[1]	values[5]	679	1			T238	22		T55	20		T74	39
auto[0]	values[1]	values[6]	422	1			T192	18		T219	17		T261	27
auto[0]	values[1]	values[7]	438	1			T69	19		T159	26		T318	20
auto[0]	values[2]	values[0]	405	1			T46	24		T312	8		T163	20
auto[0]	values[2]	values[1]	453	1			T232	168		T219	18		T225	25
auto[0]	values[2]	values[2]	731	1			T125	16		T285	8		T284	16
auto[0]	values[2]	values[3]	360	1			T67	10		T54	20		T307	2
auto[0]	values[2]	values[4]	512	1			T75	37		T194	20		T268	16
auto[0]	values[2]	values[5]	291	1			T95	8		T194	22		T163	22
auto[0]	values[2]	values[6]	513	1			T204	18		T200	8		T75	40
auto[0]	values[2]	values[7]	253	1			T293	4		T75	20		T156	48
auto[0]	values[3]	values[0]	736	1			T64	6		T75	20		T178	20
auto[0]	values[3]	values[1]	526	1			T24	8		T317	6		T260	6
auto[0]	values[3]	values[2]	454	1			T21	4		T192	20		T229	20
auto[0]	values[3]	values[3]	352	1			T61	8		T334	10		T310	20
auto[0]	values[3]	values[4]	322	1			T62	12		T178	26		T156	20
auto[0]	values[3]	values[5]	359	1			T55	20		T269	18		T75	20
auto[0]	values[3]	values[6]	457	1			T66	18		T72	17		T178	20
auto[0]	values[3]	values[7]	419	1			T229	20		T196	91		T232	20
auto[0]	values[4]	values[0]	299	1			T205	6		T196	20		T315	28
auto[0]	values[4]	values[1]	678	1			T14	10		T26	8		T54	68
auto[0]	values[4]	values[2]	428	1			T232	35		T242	21		T335	12
auto[0]	values[4]	values[3]	333	1			T75	20		T178	46		T232	29
auto[0]	values[4]	values[4]	390	1			T249	16		T259	6		T221	14
auto[0]	values[4]	values[5]	425	1			T18	8		T69	20		T73	4
auto[0]	values[4]	values[6]	502	1			T6	2		T54	20		T55	20
auto[0]	values[4]	values[7]	716	1			T244	14		T195	20		T193	23
auto[0]	values[5]	values[0]	355	1			T114	22		T197	18		T196	31
auto[0]	values[5]	values[1]	407	1			T201	6		T294	2		T75	19
auto[0]	values[5]	values[2]	411	1			T69	20		T198	14		T229	20
auto[0]	values[5]	values[3]	721	1			T69	20		T55	38		T306	10
auto[0]	values[5]	values[4]	286	1			T275	4		T287	2		T178	20
auto[0]	values[5]	values[5]	747	1			T69	18		T326	18		T279	10
auto[0]	values[5]	values[6]	359	1			T111	6		T71	4		T193	22
auto[0]	values[5]	values[7]	400	1			T193	24		T219	20		T247	18
auto[0]	values[6]	values[0]	500	1			T243	18		T69	19		T270	16
auto[0]	values[6]	values[1]	520	1			T55	39		T193	29		T298	10
auto[0]	values[6]	values[2]	375	1			T23	8		T59	18		T75	17
auto[0]	values[6]	values[3]	610	1			T267	4		T229	40		T193	35
auto[0]	values[6]	values[4]	494	1			T77	10		T264	28		T336	18
auto[0]	values[6]	values[5]	256	1			T203	16		T55	19		T304	10
auto[0]	values[6]	values[6]	491	1			T330	12		T75	20		T250	12
auto[0]	values[6]	values[7]	442	1			T60	10		T70	4		T305	2
auto[0]	values[7]	values[0]	329	1			T178	22		T196	40		T163	20
auto[0]	values[7]	values[1]	226	1			T68	8		T156	20		T225	30
auto[0]	values[7]	values[2]	326	1			T113	16		T295	12		T193	20
auto[0]	values[7]	values[3]	332	1			T139	8		T195	19		T337	8
auto[0]	values[7]	values[4]	173	1			T94	8		T338	2		T195	20
auto[0]	values[7]	values[5]	580	1			T245	12		T69	20		T55	20
auto[0]	values[7]	values[6]	238	1			T96	4		T286	20		T318	19
auto[0]	values[7]	values[7]	590	1			T63	12		T300	6		T74	50
auto[1]	values[0]	values[0]	14	1			T46	1		T69	1		T54	1
auto[1]	values[0]	values[1]	14	1			T72	1		T261	3		T292	2
auto[1]	values[0]	values[2]	10	1			T196	2		T262	3		T83	1
auto[1]	values[0]	values[3]	12	1			T69	2		T163	5		T225	1
auto[1]	values[0]	values[4]	11	1			T72	1		T193	3		T234	1
auto[1]	values[0]	values[5]	21	1			T195	2		T310	1		T181	1
auto[1]	values[0]	values[6]	18	1			T195	2		T229	2		T292	2
auto[1]	values[0]	values[7]	15	1			T246	6		T163	1		T233	1
auto[1]	values[1]	values[0]	20	1			T156	2		T196	1		T318	2
auto[1]	values[1]	values[1]	13	1			T331	2		T193	1		T310	1
auto[1]	values[1]	values[2]	4	1			T339	1		T340	1		T341	1
auto[1]	values[1]	values[3]	18	1			T195	2		T233	2		T342	3
auto[1]	values[1]	values[4]	14	1			T310	1		T182	1		T343	4
auto[1]	values[1]	values[5]	17	1			T246	3		T310	5		T225	1
auto[1]	values[1]	values[6]	14	1			T192	2		T219	3		T261	3
auto[1]	values[1]	values[7]	12	1			T69	1		T235	1		T344	1
auto[1]	values[2]	values[0]	8	1			T46	3		T345	2		T237	1
auto[1]	values[2]	values[1]	10	1			T232	3		T219	2		T225	1
auto[1]	values[2]	values[2]	11	1			T196	1		T327	2		T236	1
auto[1]	values[2]	values[3]	7	1			T346	1		T226	1		T347	4
auto[1]	values[2]	values[4]	32	1			T75	3		T268	4		T343	3
auto[1]	values[2]	values[5]	9	1			T194	1		T163	2		T348	2
auto[1]	values[2]	values[6]	17	1			T153	5		T225	1		T179	1
auto[1]	values[2]	values[7]	6	1			T292	4		T264	1		T349	1
auto[1]	values[3]	values[0]	8	1			T350	2		T232	1		T255	1
auto[1]	values[3]	values[1]	13	1			T194	1		T310	2		T340	1
auto[1]	values[3]	values[2]	6	1			T264	2		T252	1		T351	2
auto[1]	values[3]	values[3]	9	1			T352	2		T353	3		T354	4
auto[1]	values[3]	values[4]	8	1			T178	3		T343	1		T355	1
auto[1]	values[3]	values[5]	4	1			T192	1		T342	2		T355	1
auto[1]	values[3]	values[6]	21	1			T72	3		T156	1		T246	2
auto[1]	values[3]	values[7]	6	1			T196	2		T342	1		T356	1
auto[1]	values[4]	values[0]	8	1			T225	1		T262	2		T356	2
auto[1]	values[4]	values[1]	8	1			T54	2		T318	2		T355	1
auto[1]	values[4]	values[2]	9	1			T232	2		T182	1		T236	3
auto[1]	values[4]	values[3]	12	1			T178	1		T277	1		T181	3
auto[1]	values[4]	values[4]	1	1			T348	1		-	-		-	-
auto[1]	values[4]	values[5]	27	1			T73	10		T229	1		T163	1
auto[1]	values[4]	values[6]	16	1			T318	5		T83	4		T357	2
auto[1]	values[4]	values[7]	12	1			T277	1		T336	1		T226	1
auto[1]	values[5]	values[0]	17	1			T196	2		T268	2		T321	2
auto[1]	values[5]	values[1]	8	1			T75	1		T277	1		T226	1
auto[1]	values[5]	values[2]	8	1			T322	2		T246	1		T234	2
auto[1]	values[5]	values[3]	21	1			T55	2		T74	1		T247	1
auto[1]	values[5]	values[4]	1	1			T358	1		-	-		-	-
auto[1]	values[5]	values[5]	32	1			T69	2		T326	2		T292	2
auto[1]	values[5]	values[6]	8	1			T71	2		T193	1		T359	1
auto[1]	values[5]	values[7]	11	1			T247	2		T321	1		T255	1
auto[1]	values[6]	values[0]	22	1			T69	1		T246	1		T163	1
auto[1]	values[6]	values[1]	13	1			T55	1		T193	2		T310	1
auto[1]	values[6]	values[2]	15	1			T75	3		T246	1		T182	1
auto[1]	values[6]	values[3]	16	1			T319	1		T261	2		T292	1
auto[1]	values[6]	values[4]	12	1			T336	2		T251	2		T360	1
auto[1]	values[6]	values[5]	10	1			T55	1		T361	2		T324	1
auto[1]	values[6]	values[6]	6	1			T246	1		T83	1		T362	3
auto[1]	values[6]	values[7]	15	1			T70	2		T219	1		T310	4
auto[1]	values[7]	values[0]	12	1			T251	1		T363	5		T252	3
auto[1]	values[7]	values[1]	2	1			T340	1		T364	1		-	-
auto[1]	values[7]	values[2]	6	1			T182	1		T234	2		T164	1
auto[1]	values[7]	values[3]	7	1			T195	1		T264	1		T255	1
auto[1]	values[7]	values[4]	7	1			T346	4		T365	2		T366	1
auto[1]	values[7]	values[5]	12	1			T346	2		T226	2		T182	1
auto[1]	values[7]	values[6]	3	1			T318	1		T367	1		T347	1
auto[1]	values[7]	values[7]	17	1			T74	1		T247	2		T368	1