Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	838	1			T33	4		T36	17		T37	7
all_values[1]	838	1			T33	4		T36	17		T37	7
all_values[2]	838	1			T33	4		T36	17		T37	7
all_values[3]	838	1			T33	4		T36	17		T37	7
all_values[4]	838	1			T33	4		T36	17		T37	7
all_values[5]	838	1			T33	4		T36	17		T37	7
all_values[6]	838	1			T33	4		T36	17		T37	7
all_values[7]	838	1			T33	4		T36	17		T37	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3574

1

T33

21

T36

79

T37

23

auto[1]

3130

1

T33

11

T36

57

T37

33

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2671

1

T33

14

T36

59

T37

16

auto[1]

4033

1

T33

18

T36

77

T37

40

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3838

1

T33

18

T36

79

T37

28

auto[1]

2866

1

T33

14

T36

57

T37

28

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	184	1			T33	2		T36	4		T37	1
all_values[0]	auto[0]	auto[0]	auto[1]	83	1			T36	3		T37	1		T38	1
all_values[0]	auto[0]	auto[1]	auto[0]	139	1			T33	2		T36	2		T37	1
all_values[0]	auto[0]	auto[1]	auto[1]	91	1			T36	1		T37	1		T38	1
all_values[0]	auto[1]	auto[0]	auto[1]	173	1			T36	6		T37	2		T38	2
all_values[0]	auto[1]	auto[1]	auto[1]	168	1			T36	1		T37	1		T38	3
all_values[1]	auto[0]	auto[0]	auto[0]	156	1			T33	1		T36	3		T38	2
all_values[1]	auto[0]	auto[0]	auto[1]	78	1			T37	1		T39	1		T178	2
all_values[1]	auto[0]	auto[1]	auto[0]	142	1			T33	1		T36	3		T39	4
all_values[1]	auto[0]	auto[1]	auto[1]	94	1			T36	2		T37	2		T38	3
all_values[1]	auto[1]	auto[0]	auto[1]	204	1			T33	1		T36	7		T37	2
all_values[1]	auto[1]	auto[1]	auto[1]	164	1			T33	1		T36	2		T37	2
all_values[2]	auto[0]	auto[0]	auto[0]	167	1			T36	7		T37	2		T38	1
all_values[2]	auto[0]	auto[0]	auto[1]	93	1			T33	2		T39	2		T178	3
all_values[2]	auto[0]	auto[1]	auto[0]	153	1			T36	3		T37	2		T38	5
all_values[2]	auto[0]	auto[1]	auto[1]	69	1			T36	1		T38	1		T39	4
all_values[2]	auto[1]	auto[0]	auto[1]	209	1			T33	2		T36	1		T37	1
all_values[2]	auto[1]	auto[1]	auto[1]	147	1			T36	5		T37	2		T38	2
all_values[3]	auto[0]	auto[0]	auto[0]	175	1			T33	1		T36	5		T38	2
all_values[3]	auto[0]	auto[0]	auto[1]	78	1			T33	1		T36	2		T37	1
all_values[3]	auto[0]	auto[1]	auto[0]	133	1			T36	4		T37	1		T38	1
all_values[3]	auto[0]	auto[1]	auto[1]	84	1			T37	2		T38	3		T39	1
all_values[3]	auto[1]	auto[0]	auto[1]	208	1			T33	1		T36	3		T38	3
all_values[3]	auto[1]	auto[1]	auto[1]	160	1			T33	1		T36	3		T37	3
all_values[4]	auto[0]	auto[0]	auto[0]	176	1			T33	2		T36	4		T37	2
all_values[4]	auto[0]	auto[0]	auto[1]	87	1			T36	2		T38	2		T39	4
all_values[4]	auto[0]	auto[1]	auto[0]	133	1			T33	1		T36	1		T37	2
all_values[4]	auto[0]	auto[1]	auto[1]	72	1			T39	2		T178	2		T191	3
all_values[4]	auto[1]	auto[0]	auto[1]	207	1			T36	7		T37	1		T38	4
all_values[4]	auto[1]	auto[1]	auto[1]	163	1			T33	1		T36	3		T37	2
all_values[5]	auto[0]	auto[0]	auto[0]	224	1			T33	1		T36	2		T38	2
all_values[5]	auto[0]	auto[1]	auto[0]	260	1			T33	1		T36	9		T37	3
all_values[5]	auto[1]	auto[0]	auto[1]	173	1			T33	1		T36	4		T37	2
all_values[5]	auto[1]	auto[1]	auto[1]	181	1			T33	1		T36	2		T37	2
all_values[6]	auto[0]	auto[0]	auto[0]	187	1			T33	1		T36	3		T37	1
all_values[6]	auto[0]	auto[0]	auto[1]	87	1			T36	3		T39	1		T191	2
all_values[6]	auto[0]	auto[1]	auto[0]	128	1			T36	4		T37	1		T39	3
all_values[6]	auto[0]	auto[1]	auto[1]	90	1			T33	1		T36	1		T37	1
all_values[6]	auto[1]	auto[0]	auto[1]	188	1			T33	2		T36	4		T37	1
all_values[6]	auto[1]	auto[1]	auto[1]	158	1			T36	2		T37	3		T38	3
all_values[7]	auto[0]	auto[0]	auto[0]	164	1			T33	1		T36	1		T38	3
all_values[7]	auto[0]	auto[0]	auto[1]	76	1			T36	2		T37	2		T39	3
all_values[7]	auto[0]	auto[1]	auto[0]	150	1			T36	4		T38	1		T39	3
all_values[7]	auto[0]	auto[1]	auto[1]	85	1			T36	3		T37	1		T38	1
all_values[7]	auto[1]	auto[0]	auto[1]	197	1			T33	2		T36	6		T37	3
all_values[7]	auto[1]	auto[1]	auto[1]	166	1			T33	1		T36	1		T37	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal