Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1812

1

T3

2

T4

1

T15

4

auto[1]

1779

1

T3

6

T12

1

T15

1

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1944

1

T4

1

T48

4

T46

1

auto[1]

1647

1

T3

8

T12

1

T15

5

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2823

1

T3

8

T12

1

T15

5

auto[1]

768

1

T4

1

T48

1

T47

5

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	724	1			T3	3		T4	1		T15	1
valid[1]	712	1			T3	1		T17	1		T27	1
valid[2]	699	1			T15	2		T17	1		T28	5
valid[3]	723	1			T3	2		T12	1		T15	2
valid[4]	733	1			T3	2		T17	2		T27	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	121	1			T82	4		T108	2		T387	1
auto[0]	auto[0]	valid[0]	auto[1]	170	1			T28	8		T76	3		T81	3
auto[0]	auto[0]	valid[1]	auto[0]	114	1			T48	1		T47	1		T58	1
auto[0]	auto[0]	valid[1]	auto[1]	149	1			T17	1		T27	1		T28	3
auto[0]	auto[0]	valid[2]	auto[0]	137	1			T47	1		T397	2		T82	1
auto[0]	auto[0]	valid[2]	auto[1]	155	1			T15	2		T28	4		T30	5
auto[0]	auto[0]	valid[3]	auto[0]	120	1			T82	2		T108	2		T42	1
auto[0]	auto[0]	valid[3]	auto[1]	159	1			T3	1		T15	2		T28	3
auto[0]	auto[0]	valid[4]	auto[0]	126	1			T46	1		T47	1		T109	3
auto[0]	auto[0]	valid[4]	auto[1]	172	1			T3	1		T17	2		T28	1
auto[0]	auto[1]	valid[0]	auto[0]	104	1			T48	1		T47	1		T387	1
auto[0]	auto[1]	valid[0]	auto[1]	171	1			T3	3		T15	1		T17	1
auto[0]	auto[1]	valid[1]	auto[0]	112	1			T48	1		T47	1		T109	4
auto[0]	auto[1]	valid[1]	auto[1]	190	1			T3	1		T28	4		T30	4
auto[0]	auto[1]	valid[2]	auto[0]	99	1			T58	1		T109	1		T82	2
auto[0]	auto[1]	valid[2]	auto[1]	153	1			T17	1		T28	1		T30	3
auto[0]	auto[1]	valid[3]	auto[0]	124	1			T109	2		T82	1		T108	1
auto[0]	auto[1]	valid[3]	auto[1]	157	1			T3	1		T12	1		T17	3
auto[0]	auto[1]	valid[4]	auto[0]	119	1			T47	1		T42	1		T187	2
auto[0]	auto[1]	valid[4]	auto[1]	171	1			T3	1		T27	1		T28	2
auto[1]	auto[0]	valid[0]	auto[0]	78	1			T4	1		T379	1		T187	2
auto[1]	auto[0]	valid[1]	auto[0]	84	1			T47	1		T109	2		T82	2
auto[1]	auto[0]	valid[2]	auto[0]	75	1			T109	1		T82	1		T108	1
auto[1]	auto[0]	valid[3]	auto[0]	78	1			T47	1		T82	1		T108	1
auto[1]	auto[0]	valid[4]	auto[0]	74	1			T47	1		T108	2		T38	1
auto[1]	auto[1]	valid[0]	auto[0]	80	1			T109	1		T82	1		T42	1
auto[1]	auto[1]	valid[1]	auto[0]	63	1			T48	1		T82	1		T42	1
auto[1]	auto[1]	valid[2]	auto[0]	80	1			T47	1		T108	1		T42	2
auto[1]	auto[1]	valid[3]	auto[0]	85	1			T109	1		T82	2		T42	1
auto[1]	auto[1]	valid[4]	auto[0]	71	1			T47	1		T387	1		T93	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal