Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48599

1

T4

6

T12

26

T16

2

auto[1]

18035

1

T3

8

T12

9

T15

5

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48950

1

T3

8

T4

1

T12

22

auto[1]

17684

1

T4

5

T12

13

T16

1

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	34262	1			T3	8		T4	1		T12	24
others[1]	5522	1			T12	3		T17	6		T28	23
others[2]	5639	1			T4	1		T12	1		T17	6
others[3]	6458	1			T4	2		T12	2		T17	12
interest[1]	3833	1			T12	2		T17	6		T28	17
interest[4]	22413	1			T3	8		T4	1		T12	12
interest[64]	10920	1			T4	2		T12	3		T17	9

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15829	1			T12	13		T16	1		T29	4
auto[0]	auto[0]	others[1]	2596	1			T29	2		T48	2		T46	7
auto[0]	auto[0]	others[2]	2633	1			T29	1		T48	6		T46	3
auto[0]	auto[0]	others[3]	3065	1			T48	7		T46	8		T47	14
auto[0]	auto[0]	interest[1]	1772	1			T48	3		T47	4		T58	8
auto[0]	auto[0]	interest[4]	10322	1			T12	5		T16	1		T29	3
auto[0]	auto[0]	interest[64]	5020	1			T4	1		T29	2		T48	18
auto[0]	auto[1]	others[0]	9376	1			T3	8		T12	3		T15	5
auto[0]	auto[1]	others[1]	1404	1			T12	1		T17	6		T28	23
auto[0]	auto[1]	others[2]	1516	1			T17	6		T28	38		T30	23
auto[0]	auto[1]	others[3]	1725	1			T12	2		T17	12		T28	25
auto[0]	auto[1]	interest[1]	1006	1			T17	6		T28	17		T30	22
auto[0]	auto[1]	interest[4]	6241	1			T3	8		T12	2		T15	5
auto[0]	auto[1]	interest[64]	3008	1			T12	3		T17	9		T28	67
auto[1]	auto[0]	others[0]	9057	1			T4	1		T12	8		T16	1
auto[1]	auto[0]	others[1]	1522	1			T12	2		T48	1		T50	1
auto[1]	auto[0]	others[2]	1490	1			T4	1		T12	1		T48	1
auto[1]	auto[0]	others[3]	1668	1			T4	2		T48	3		T46	2
auto[1]	auto[0]	interest[1]	1055	1			T12	2		T48	2		T46	6
auto[1]	auto[0]	interest[4]	5850	1			T4	1		T12	5		T16	1
auto[1]	auto[0]	interest[64]	2892	1			T4	1		T29	1		T48	5

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal