Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2276194	1			T1	1		T2	1		T4	1
all_values[1]	2276194	1			T1	1		T2	1		T4	1
all_values[2]	2276194	1			T1	1		T2	1		T4	1
all_values[3]	2276194	1			T1	1		T2	1		T4	1
all_values[4]	2276194	1			T1	1		T2	1		T4	1
all_values[5]	2276194	1			T1	1		T2	1		T4	1
all_values[6]	2276194	1			T1	1		T2	1		T4	1
all_values[7]	2276194	1			T1	1		T2	1		T4	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17704285

1

T1

8

T2

8

T4

8

auto[1]

505267

1

T36

30

T37

41

T38

5606

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18186479

1

T1

8

T2

8

T4

8

auto[1]

23073

1

T32

221

T102

1

T50

231

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2142573	1			T1	1		T2	1		T4	1
all_values[0]	auto[0]	auto[1]	9840	1			T32	100		T50	103		T23	64
all_values[0]	auto[1]	auto[0]	122975	1			T36	4		T37	1		T38	1073
all_values[0]	auto[1]	auto[1]	806	1			T37	6		T38	38		T39	3
all_values[1]	auto[0]	auto[0]	2229352	1			T1	1		T2	1		T4	1
all_values[1]	auto[0]	auto[1]	6797	1			T32	100		T50	92		T23	41
all_values[1]	auto[1]	auto[0]	39690	1			T36	5		T37	1		T38	1095
all_values[1]	auto[1]	auto[1]	355	1			T37	7		T38	24		T39	3
all_values[2]	auto[0]	auto[0]	2202567	1			T1	1		T2	1		T4	1
all_values[2]	auto[0]	auto[1]	2914	1			T32	21		T50	36		T23	13
all_values[2]	auto[1]	auto[0]	70427	1			T37	3		T38	3		T39	3
all_values[2]	auto[1]	auto[1]	286	1			T36	1		T38	4		T39	4
all_values[3]	auto[0]	auto[0]	2268973	1			T1	1		T2	1		T4	1
all_values[3]	auto[0]	auto[1]	215	1			T37	5		T38	8		T39	1
all_values[3]	auto[1]	auto[0]	6790	1			T37	2		T38	9		T39	4
all_values[3]	auto[1]	auto[1]	216	1			T36	1		T38	3		T39	4
all_values[4]	auto[0]	auto[0]	2164398	1			T1	1		T2	1		T4	1
all_values[4]	auto[0]	auto[1]	225	1			T102	1		T37	3		T38	3
all_values[4]	auto[1]	auto[0]	111362	1			T36	6		T37	4		T38	1112
all_values[4]	auto[1]	auto[1]	209	1			T37	1		T38	6		T39	2
all_values[5]	auto[0]	auto[0]	2216035	1			T1	1		T2	1		T4	1
all_values[5]	auto[0]	auto[1]	205	1			T37	3		T38	5		T39	4
all_values[5]	auto[1]	auto[0]	59767	1			T37	3		T38	1116		T39	3
all_values[5]	auto[1]	auto[1]	187	1			T36	2		T37	2		T38	2
all_values[6]	auto[0]	auto[0]	2256314	1			T1	1		T2	1		T4	1
all_values[6]	auto[0]	auto[1]	220	1			T36	1		T37	2		T38	5
all_values[6]	auto[1]	auto[0]	19468	1			T36	2		T37	2		T38	1108
all_values[6]	auto[1]	auto[1]	192	1			T36	3		T37	2		T38	7
all_values[7]	auto[0]	auto[0]	2203454	1			T1	1		T2	1		T4	1
all_values[7]	auto[0]	auto[1]	203	1			T37	2		T38	8		T39	2
all_values[7]	auto[1]	auto[0]	72334	1			T36	5		T37	3		T38	3
all_values[7]	auto[1]	auto[1]	203	1			T36	1		T37	4		T38	3