Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.77 98.70 96.92 99.01 89.36 98.59 95.56 99.26


Total tests in report: 1151
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
64.75 64.75 92.56 92.56 82.85 82.85 83.20 83.20 26.67 26.67 90.16 90.16 72.08 72.08 5.74 5.74 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_intercept.717615708
79.26 14.51 97.02 4.46 91.78 8.93 87.75 4.55 73.33 46.67 96.50 6.33 84.31 12.22 24.16 18.42 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.3097892839
84.40 5.14 97.40 0.37 92.42 0.64 87.85 0.10 86.67 13.33 97.08 0.58 84.58 0.28 44.80 20.64 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_and_tpm.4198864506
87.16 2.76 97.79 0.39 93.45 1.02 90.12 2.27 86.67 0.00 97.51 0.43 84.86 0.28 59.75 14.95 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_stress_all.1375494061
89.41 2.25 98.02 0.23 93.79 0.35 90.71 0.59 91.11 4.44 97.77 0.26 85.42 0.56 69.06 9.31 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_all.1185481561
90.99 1.58 98.04 0.02 93.99 0.19 91.70 0.99 91.11 0.00 97.80 0.03 93.75 8.33 70.54 1.49 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.1595281167
91.91 0.92 98.15 0.11 94.07 0.09 92.09 0.40 93.33 2.22 97.89 0.09 93.75 0.00 74.06 3.51 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_mode_ignore_cmds.3457015935
92.65 0.75 98.37 0.21 94.09 0.01 96.94 4.84 93.33 0.00 98.04 0.15 93.75 0.00 74.06 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_ram_cfg.176422985
93.25 0.59 98.39 0.02 94.11 0.03 96.94 0.00 93.33 0.00 98.04 0.00 93.75 0.00 78.17 4.11 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_stress_all.2545899083
93.75 0.51 98.41 0.03 94.15 0.04 96.94 0.00 93.33 0.00 98.11 0.07 93.75 0.00 81.58 3.42 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_and_tpm_min_idle.3345313345
94.18 0.43 98.61 0.20 95.33 1.18 97.23 0.30 93.33 0.00 98.44 0.33 94.31 0.56 82.03 0.45 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_mode.2386029087
94.56 0.37 98.61 0.00 95.33 0.00 97.23 0.00 93.33 0.00 98.44 0.00 94.31 0.00 84.65 2.62 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_and_tpm.2171640991
94.89 0.33 98.61 0.00 96.17 0.84 97.23 0.00 93.33 0.00 98.47 0.03 94.44 0.14 85.94 1.29 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.1703320777
95.20 0.32 98.61 0.00 96.20 0.03 97.23 0.00 93.33 0.00 98.49 0.02 94.44 0.00 88.12 2.18 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.2694328048
95.44 0.24 98.61 0.00 96.20 0.00 97.23 0.00 93.33 0.00 98.49 0.00 94.44 0.00 89.80 1.68 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_all.1983548637
95.67 0.23 98.61 0.00 96.22 0.03 98.42 1.19 93.33 0.00 98.49 0.00 94.58 0.14 90.05 0.25 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_sec_cm.3425683892
95.86 0.18 98.61 0.00 96.22 0.00 98.42 0.00 93.33 0.00 98.49 0.00 94.58 0.00 91.34 1.29 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_and_tpm_min_idle.1360428426
96.02 0.16 98.61 0.00 96.22 0.00 98.42 0.00 93.33 0.00 98.49 0.00 94.58 0.00 92.48 1.14 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_all.914865416
96.14 0.12 98.61 0.00 96.25 0.03 98.42 0.00 93.33 0.00 98.49 0.00 95.42 0.83 92.48 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1686723383
96.26 0.12 98.61 0.00 96.25 0.00 98.42 0.00 93.33 0.00 98.49 0.00 95.42 0.00 93.32 0.84 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_all.1132948667
96.37 0.11 98.61 0.00 96.25 0.00 98.42 0.00 93.33 0.00 98.49 0.00 95.42 0.00 94.06 0.74 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_and_tpm_min_idle.2439728391
96.47 0.10 98.61 0.00 96.25 0.00 98.42 0.00 93.33 0.00 98.49 0.00 95.42 0.00 94.75 0.69 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_and_tpm_min_idle.4086728978
96.56 0.10 98.67 0.06 96.39 0.14 98.81 0.40 93.33 0.00 98.58 0.09 95.42 0.00 94.75 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_mem_parity.2881568566
96.63 0.07 98.67 0.00 96.39 0.00 98.81 0.00 93.33 0.00 98.58 0.00 95.42 0.00 95.25 0.50 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_and_tpm_min_idle.896146060
96.69 0.06 98.67 0.00 96.39 0.00 98.81 0.00 93.33 0.00 98.58 0.00 95.42 0.00 95.64 0.40 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_and_tpm.17447339
96.75 0.06 98.67 0.00 96.39 0.00 98.81 0.00 93.33 0.00 98.58 0.00 95.42 0.00 96.04 0.40 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_and_tpm_min_idle.1338977031
96.80 0.05 98.67 0.00 96.75 0.36 98.81 0.00 93.33 0.00 98.58 0.00 95.42 0.00 96.04 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_read_buffer_direct.2572507005
96.85 0.05 98.67 0.00 96.75 0.00 98.81 0.00 93.33 0.00 98.58 0.00 95.56 0.14 96.24 0.20 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/22.spi_device_stress_all.1079196915
96.89 0.04 98.67 0.00 96.75 0.00 98.81 0.00 93.33 0.00 98.58 0.00 95.56 0.00 96.53 0.30 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_and_tpm.2912831290
96.93 0.04 98.67 0.00 96.75 0.00 98.81 0.00 93.33 0.00 98.58 0.00 95.56 0.00 96.83 0.30 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_mode_ignore_cmds.2656131055
96.97 0.04 98.69 0.03 96.79 0.04 99.01 0.20 93.33 0.00 98.58 0.00 95.56 0.00 96.83 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_alert_test.607898814
97.01 0.04 98.69 0.00 96.79 0.00 99.01 0.00 93.33 0.00 98.58 0.00 95.56 0.00 97.08 0.25 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm.2015902306
97.03 0.03 98.69 0.00 96.79 0.00 99.01 0.00 93.33 0.00 98.58 0.00 95.56 0.00 97.28 0.20 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_intg_err.3937186570
97.06 0.03 98.69 0.00 96.79 0.00 99.01 0.00 93.33 0.00 98.58 0.00 95.56 0.00 97.48 0.20 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_stress_all.1500479788
97.09 0.03 98.69 0.00 96.79 0.00 99.01 0.00 93.33 0.00 98.58 0.00 95.56 0.00 97.67 0.20 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_and_tpm_min_idle.2438068111
97.12 0.03 98.69 0.00 96.79 0.00 99.01 0.00 93.33 0.00 98.58 0.00 95.56 0.00 97.87 0.20 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_and_tpm.3302283013
97.14 0.02 98.69 0.00 96.79 0.00 99.01 0.00 93.33 0.00 98.58 0.00 95.56 0.00 98.02 0.15 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_read_hw_reg.3195242096
97.16 0.02 98.69 0.00 96.79 0.00 99.01 0.00 93.33 0.00 98.58 0.00 95.56 0.00 98.17 0.15 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_mode.4182915339
97.18 0.02 98.69 0.00 96.85 0.06 99.01 0.00 93.33 0.00 98.58 0.00 95.56 0.00 98.22 0.05 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.1908833665
97.19 0.01 98.69 0.00 96.85 0.00 99.01 0.00 93.33 0.00 98.58 0.00 95.56 0.00 98.32 0.10 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.3604599765
97.21 0.01 98.69 0.00 96.85 0.00 99.01 0.00 93.33 0.00 98.58 0.00 95.56 0.00 98.42 0.10 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_all.4112817594
97.22 0.01 98.69 0.00 96.85 0.00 99.01 0.00 93.33 0.00 98.58 0.00 95.56 0.00 98.51 0.10 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_all.1624895317
97.23 0.01 98.69 0.00 96.85 0.00 99.01 0.00 93.33 0.00 98.58 0.00 95.56 0.00 98.61 0.10 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_and_tpm_min_idle.2291317947
97.25 0.01 98.69 0.00 96.85 0.00 99.01 0.00 93.33 0.00 98.58 0.00 95.56 0.00 98.71 0.10 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_and_tpm.1061305179
97.26 0.01 98.69 0.00 96.85 0.00 99.01 0.00 93.33 0.00 98.58 0.00 95.56 0.00 98.81 0.10 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_all.4128651624
97.27 0.01 98.69 0.00 96.85 0.00 99.01 0.00 93.33 0.00 98.58 0.00 95.56 0.00 98.86 0.05 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_mode_ignore_cmds.3749435729
97.28 0.01 98.69 0.00 96.85 0.00 99.01 0.00 93.33 0.00 98.58 0.00 95.56 0.00 98.91 0.05 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_upload.2257372381
97.28 0.01 98.69 0.00 96.85 0.00 99.01 0.00 93.33 0.00 98.58 0.00 95.56 0.00 98.96 0.05 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_mode_ignore_cmds.2461403369
97.29 0.01 98.69 0.00 96.85 0.00 99.01 0.00 93.33 0.00 98.58 0.00 95.56 0.00 99.01 0.05 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_and_tpm.2277270920
97.30 0.01 98.69 0.00 96.85 0.00 99.01 0.00 93.33 0.00 98.58 0.00 95.56 0.00 99.06 0.05 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/17.spi_device_stress_all.982275739
97.30 0.01 98.69 0.00 96.85 0.00 99.01 0.00 93.33 0.00 98.58 0.00 95.56 0.00 99.11 0.05 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_mode.3906223820
97.31 0.01 98.69 0.00 96.85 0.00 99.01 0.00 93.33 0.00 98.58 0.00 95.56 0.00 99.16 0.05 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_and_tpm_min_idle.910733815
97.32 0.01 98.69 0.00 96.85 0.00 99.01 0.00 93.33 0.00 98.58 0.00 95.56 0.00 99.21 0.05 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_mode.4150162202
97.33 0.01 98.69 0.00 96.85 0.00 99.01 0.00 93.33 0.00 98.58 0.00 95.56 0.00 99.26 0.05 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_mode.82994750
97.33 0.01 98.70 0.01 96.85 0.00 99.01 0.00 93.33 0.00 98.59 0.02 95.56 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_pass_cmd_filtering.274442788
97.33 0.01 98.70 0.00 96.88 0.03 99.01 0.00 93.33 0.00 98.59 0.00 95.56 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_errors.139131125
97.33 0.01 98.70 0.00 96.89 0.01 99.01 0.00 93.33 0.00 98.59 0.00 95.56 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_intg_err.617346853
97.34 0.01 98.70 0.00 96.90 0.01 99.01 0.00 93.33 0.00 98.59 0.00 95.56 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_intg_err.105633441
97.34 0.01 98.70 0.00 96.92 0.01 99.01 0.00 93.33 0.00 98.59 0.00 95.56 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_and_tpm_min_idle.3119642053

Tests that do not contribute to grading

Name   
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.658600789
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2409560343
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2924133842
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2509145695
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.3307455069
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.1898658176
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.3232368835
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.2030362849
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1692657791
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.2026432019
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.419859730
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2783875492
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.951282633
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.2399349307
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.4060777320
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.3203838434
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.1708573437
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3859236568
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.1101908553
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2911656924
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.94319275
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.251834494
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.633694477
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.3389873272
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3497459377
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_rw.2421185105
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_intr_test.1551377090
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/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_pass_cmd_filtering.3237225243
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_read_buffer_direct.2002069245
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_stress_all.4273190678
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_all.2191355480
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_read_hw_reg.3272566508
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_rw.429090349
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.146816793
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_upload.501021235
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_alert_test.1006733628
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_cfg_cmd.1813410022
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_csb_read.238356075
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_all.1460667608
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm.1912643143
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.1035787076
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode.698648407
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode_ignore_cmds.2117034002
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_intercept.2304175531
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mailbox.5735935
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mem_parity.1977117361
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.3105777342
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.3976870842
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.277287902
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_stress_all.846158665
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_all.2513268032
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.3287257460
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_rw.15019582
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.1343753080
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_upload.2304127487
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_alert_test.644915437
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_cfg_cmd.1633673782
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_csb_read.124743128
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_all.462315329
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.3433429135
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode.2050359194
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_intercept.2034667748
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mailbox.4192523383
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mem_parity.592440658
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.222924052
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.3215309422
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.1142446050
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_stress_all.2857562893
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_all.3281427922
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.725112337
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_rw.51879791
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_sts_read.3694924587
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_upload.1860303313
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_alert_test.3120677781
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_cfg_cmd.1460783382
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_csb_read.2118969038
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_all.3159463407
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_and_tpm.342589645
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode.374100141
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.247149701
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_intercept.1095866254
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mailbox.2344338262
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mem_parity.1097914213
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.356838000
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.1841350878
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.858520638
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_stress_all.3153685188
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_all.1534311636
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.3920687842
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_rw.2804543471
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.54115675
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_upload.360028977



Total test records in report: 1151
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_csb_read.3395767869 Oct 09 03:53:23 PM UTC 24 Oct 09 03:53:26 PM UTC 24 64606014 ps
T2 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_ram_cfg.176422985 Oct 09 03:53:26 PM UTC 24 Oct 09 03:53:29 PM UTC 24 25638421 ps
T3 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_mem_parity.2904679441 Oct 09 03:53:26 PM UTC 24 Oct 09 03:53:29 PM UTC 24 18605603 ps
T4 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_sts_read.2349938739 Oct 09 03:53:30 PM UTC 24 Oct 09 03:53:32 PM UTC 24 12842900 ps
T5 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_rw.3732148728 Oct 09 03:53:33 PM UTC 24 Oct 09 03:53:35 PM UTC 24 11521875 ps
T6 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_all.1348905652 Oct 09 03:53:30 PM UTC 24 Oct 09 03:53:45 PM UTC 24 4083058550 ps
T7 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_pass_cmd_filtering.274442788 Oct 09 03:53:36 PM UTC 24 Oct 09 03:53:48 PM UTC 24 1974471812 ps
T8 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_pass_addr_payload_swap.114261137 Oct 09 03:53:46 PM UTC 24 Oct 09 03:53:52 PM UTC 24 157185209 ps
T9 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_intercept.717615708 Oct 09 03:53:48 PM UTC 24 Oct 09 03:53:58 PM UTC 24 573077823 ps
T10 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_read_hw_reg.3195242096 Oct 09 03:53:30 PM UTC 24 Oct 09 03:54:00 PM UTC 24 17602022981 ps
T11 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_cfg_cmd.251879324 Oct 09 03:53:54 PM UTC 24 Oct 09 03:54:01 PM UTC 24 71785249 ps
T12 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_mode.2386029087 Oct 09 03:53:59 PM UTC 24 Oct 09 03:54:06 PM UTC 24 141263611 ps
T13 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_upload.3123525522 Oct 09 03:53:52 PM UTC 24 Oct 09 03:54:06 PM UTC 24 1038437066 ps
T14 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_read_buffer_direct.1116109403 Oct 09 03:54:01 PM UTC 24 Oct 09 03:54:12 PM UTC 24 2317675689 ps
T15 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_sec_cm.3425683892 Oct 09 03:54:19 PM UTC 24 Oct 09 03:54:21 PM UTC 24 75297431 ps
T24 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_alert_test.607898814 Oct 09 03:54:21 PM UTC 24 Oct 09 03:54:23 PM UTC 24 14334719 ps
T16 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_csb_read.117889166 Oct 09 03:54:22 PM UTC 24 Oct 09 03:54:24 PM UTC 24 40871309 ps
T25 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_mem_parity.338510606 Oct 09 03:54:22 PM UTC 24 Oct 09 03:54:25 PM UTC 24 26836134 ps
T26 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_sts_read.2539781199 Oct 09 03:54:25 PM UTC 24 Oct 09 03:54:28 PM UTC 24 54745806 ps
T27 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_rw.1647224125 Oct 09 03:54:28 PM UTC 24 Oct 09 03:54:32 PM UTC 24 642641145 ps
T40 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_pass_cmd_filtering.1957325475 Oct 09 03:54:32 PM UTC 24 Oct 09 03:54:37 PM UTC 24 29750210 ps
T17 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_pass_addr_payload_swap.287005786 Oct 09 03:54:34 PM UTC 24 Oct 09 03:54:39 PM UTC 24 431016091 ps
T18 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_intercept.1316744586 Oct 09 03:54:38 PM UTC 24 Oct 09 03:54:42 PM UTC 24 138497757 ps
T28 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_all.1185481561 Oct 09 03:54:25 PM UTC 24 Oct 09 03:54:49 PM UTC 24 1318050630 ps
T19 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_all.1468956522 Oct 09 03:54:02 PM UTC 24 Oct 09 03:54:50 PM UTC 24 3538550602 ps
T55 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_cfg_cmd.1132541561 Oct 09 03:54:47 PM UTC 24 Oct 09 03:54:53 PM UTC 24 200946222 ps
T29 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_read_hw_reg.533370925 Oct 09 03:54:24 PM UTC 24 Oct 09 03:54:56 PM UTC 24 27476428106 ps
T51 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_mailbox.1895763763 Oct 09 03:53:52 PM UTC 24 Oct 09 03:54:57 PM UTC 24 20894744833 ps
T56 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_upload.2257372381 Oct 09 03:54:43 PM UTC 24 Oct 09 03:55:04 PM UTC 24 5250091916 ps
T45 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_mode.697905620 Oct 09 03:54:50 PM UTC 24 Oct 09 03:55:07 PM UTC 24 2152416751 ps
T30 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_and_tpm_min_idle.649899116 Oct 09 03:54:07 PM UTC 24 Oct 09 03:55:08 PM UTC 24 14378522356 ps
T20 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_sec_cm.955923705 Oct 09 03:55:06 PM UTC 24 Oct 09 03:55:08 PM UTC 24 242267621 ps
T31 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_csb_read.2990822191 Oct 09 03:55:08 PM UTC 24 Oct 09 03:55:10 PM UTC 24 52227808 ps
T83 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_alert_test.936454451 Oct 09 03:55:08 PM UTC 24 Oct 09 03:55:11 PM UTC 24 13371254 ps
T32 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.3097892839 Oct 09 03:54:06 PM UTC 24 Oct 09 03:55:11 PM UTC 24 13333731374 ps
T44 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_mem_parity.559028328 Oct 09 03:55:09 PM UTC 24 Oct 09 03:55:12 PM UTC 24 45236340 ps
T33 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_sts_read.3924398330 Oct 09 03:55:12 PM UTC 24 Oct 09 03:55:14 PM UTC 24 75155402 ps
T34 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_rw.1002751629 Oct 09 03:55:13 PM UTC 24 Oct 09 03:55:16 PM UTC 24 147919830 ps
T52 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_read_buffer_direct.2572507005 Oct 09 03:54:53 PM UTC 24 Oct 09 03:55:16 PM UTC 24 6888598667 ps
T115 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_pass_addr_payload_swap.3782445779 Oct 09 03:55:15 PM UTC 24 Oct 09 03:55:19 PM UTC 24 762047606 ps
T53 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_pass_cmd_filtering.122549673 Oct 09 03:55:13 PM UTC 24 Oct 09 03:55:20 PM UTC 24 688652128 ps
T94 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_read_hw_reg.1844013908 Oct 09 03:55:09 PM UTC 24 Oct 09 03:55:27 PM UTC 24 6117139268 ps
T125 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_cfg_cmd.1486749578 Oct 09 03:55:21 PM UTC 24 Oct 09 03:55:30 PM UTC 24 494963618 ps
T54 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_mode_ignore_cmds.3457015935 Oct 09 03:53:59 PM UTC 24 Oct 09 03:55:36 PM UTC 24 11909567966 ps
T126 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_read_buffer_direct.2730329698 Oct 09 03:55:37 PM UTC 24 Oct 09 03:55:43 PM UTC 24 103637709 ps
T101 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_upload.3160575715 Oct 09 03:55:20 PM UTC 24 Oct 09 03:55:43 PM UTC 24 5725922094 ps
T222 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_mailbox.3825405431 Oct 09 03:54:40 PM UTC 24 Oct 09 03:55:45 PM UTC 24 7337743104 ps
T63 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_all.2314771049 Oct 09 03:55:12 PM UTC 24 Oct 09 03:55:47 PM UTC 24 17563903187 ps
T102 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_mode.3906223820 Oct 09 03:55:28 PM UTC 24 Oct 09 03:55:48 PM UTC 24 509116997 ps
T84 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_alert_test.1458091081 Oct 09 03:55:50 PM UTC 24 Oct 09 03:55:52 PM UTC 24 21225242 ps
T21 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_sec_cm.2419786980 Oct 09 03:55:49 PM UTC 24 Oct 09 03:55:52 PM UTC 24 159471580 ps
T363 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_csb_read.3501956469 Oct 09 03:55:53 PM UTC 24 Oct 09 03:55:55 PM UTC 24 42700432 ps
T57 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_mailbox.1803120751 Oct 09 03:55:17 PM UTC 24 Oct 09 03:55:56 PM UTC 24 3407717014 ps
T364 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_mem_parity.2881568566 Oct 09 03:55:54 PM UTC 24 Oct 09 03:55:56 PM UTC 24 27390432 ps
T103 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_intercept.1675256723 Oct 09 03:55:16 PM UTC 24 Oct 09 03:55:59 PM UTC 24 38168430900 ps
T95 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_sts_read.621425545 Oct 09 03:55:57 PM UTC 24 Oct 09 03:56:00 PM UTC 24 321148490 ps
T96 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_read_hw_reg.2130498334 Oct 09 03:55:56 PM UTC 24 Oct 09 03:56:01 PM UTC 24 415555185 ps
T64 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_rw.1440191335 Oct 09 03:55:59 PM UTC 24 Oct 09 03:56:03 PM UTC 24 269023280 ps
T175 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_pass_addr_payload_swap.1295465911 Oct 09 03:56:01 PM UTC 24 Oct 09 03:56:06 PM UTC 24 147792934 ps
T183 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_intercept.975698187 Oct 09 03:56:05 PM UTC 24 Oct 09 03:56:12 PM UTC 24 123808985 ps
T105 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_pass_cmd_filtering.3876421518 Oct 09 03:56:00 PM UTC 24 Oct 09 03:56:13 PM UTC 24 5785600897 ps
T365 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_cfg_cmd.3929673954 Oct 09 03:56:14 PM UTC 24 Oct 09 03:56:19 PM UTC 24 198069886 ps
T176 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_upload.2247205697 Oct 09 03:56:13 PM UTC 24 Oct 09 03:56:32 PM UTC 24 3222220841 ps
T65 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_all.1168302362 Oct 09 03:55:57 PM UTC 24 Oct 09 03:56:32 PM UTC 24 2292648055 ps
T152 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_read_buffer_direct.2765882312 Oct 09 03:56:32 PM UTC 24 Oct 09 03:56:39 PM UTC 24 128865193 ps
T153 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_mode.2901131578 Oct 09 03:56:20 PM UTC 24 Oct 09 03:56:40 PM UTC 24 2770977629 ps
T104 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_mailbox.525068359 Oct 09 03:56:07 PM UTC 24 Oct 09 03:56:52 PM UTC 24 5161052963 ps
T22 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_sec_cm.3109463055 Oct 09 03:56:53 PM UTC 24 Oct 09 03:56:56 PM UTC 24 281813247 ps
T366 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_alert_test.496008285 Oct 09 03:56:56 PM UTC 24 Oct 09 03:56:58 PM UTC 24 21835333 ps
T367 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_csb_read.2785087772 Oct 09 03:56:59 PM UTC 24 Oct 09 03:57:01 PM UTC 24 16526789 ps
T368 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_mem_parity.1671917279 Oct 09 03:57:02 PM UTC 24 Oct 09 03:57:05 PM UTC 24 42437339 ps
T369 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_read_hw_reg.2908662794 Oct 09 03:57:05 PM UTC 24 Oct 09 03:57:21 PM UTC 24 946848827 ps
T370 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_sts_read.695023460 Oct 09 03:57:23 PM UTC 24 Oct 09 03:57:25 PM UTC 24 28452346 ps
T82 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_rw.334647930 Oct 09 03:57:26 PM UTC 24 Oct 09 03:57:29 PM UTC 24 626025772 ps
T260 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_pass_addr_payload_swap.3370551859 Oct 09 03:57:30 PM UTC 24 Oct 09 03:57:35 PM UTC 24 118621252 ps
T346 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_all.484589503 Oct 09 03:57:23 PM UTC 24 Oct 09 03:57:37 PM UTC 24 755738943 ps
T106 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_pass_cmd_filtering.3608171280 Oct 09 03:57:27 PM UTC 24 Oct 09 03:57:39 PM UTC 24 1790295966 ps
T49 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_all.1996740433 Oct 09 03:56:33 PM UTC 24 Oct 09 03:57:42 PM UTC 24 2398076129 ps
T227 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_intercept.354756229 Oct 09 03:57:36 PM UTC 24 Oct 09 03:57:42 PM UTC 24 652595846 ps
T50 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_and_tpm.2912831290 Oct 09 03:54:59 PM UTC 24 Oct 09 03:57:44 PM UTC 24 16635351182 ps
T184 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_upload.3221052080 Oct 09 03:57:39 PM UTC 24 Oct 09 03:57:46 PM UTC 24 1134774955 ps
T259 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_cfg_cmd.3372215107 Oct 09 03:57:44 PM UTC 24 Oct 09 03:57:49 PM UTC 24 134415291 ps
T81 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_mode_ignore_cmds.1836759584 Oct 09 03:56:22 PM UTC 24 Oct 09 03:57:52 PM UTC 24 4031768669 ps
T23 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_stress_all.123996981 Oct 09 03:56:41 PM UTC 24 Oct 09 03:57:56 PM UTC 24 1935360778 ps
T154 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_read_buffer_direct.3167095778 Oct 09 03:57:47 PM UTC 24 Oct 09 03:58:00 PM UTC 24 2956183123 ps
T46 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_and_tpm.4198864506 Oct 09 03:55:44 PM UTC 24 Oct 09 03:58:00 PM UTC 24 7045084599 ps
T35 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_sec_cm.3080029469 Oct 09 03:57:59 PM UTC 24 Oct 09 03:58:01 PM UTC 24 115725807 ps
T138 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_mode.691303294 Oct 09 03:57:44 PM UTC 24 Oct 09 03:58:02 PM UTC 24 1082352392 ps
T139 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_alert_test.2113291052 Oct 09 03:58:01 PM UTC 24 Oct 09 03:58:03 PM UTC 24 24226892 ps
T140 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/5.spi_device_csb_read.1763217232 Oct 09 03:58:02 PM UTC 24 Oct 09 03:58:04 PM UTC 24 78283617 ps
T141 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/5.spi_device_mem_parity.2517593394 Oct 09 03:58:02 PM UTC 24 Oct 09 03:58:04 PM UTC 24 50710994 ps
T142 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_sts_read.3731978792 Oct 09 03:58:04 PM UTC 24 Oct 09 03:58:07 PM UTC 24 42528081 ps
T143 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/5.spi_device_pass_cmd_filtering.3237821657 Oct 09 03:58:05 PM UTC 24 Oct 09 03:58:10 PM UTC 24 216938708 ps
T144 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_rw.2053083488 Oct 09 03:58:05 PM UTC 24 Oct 09 03:58:11 PM UTC 24 749013375 ps
T47 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_all.4112817594 Oct 09 03:54:58 PM UTC 24 Oct 09 03:58:12 PM UTC 24 90407173498 ps
T245 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/5.spi_device_intercept.981090614 Oct 09 03:58:11 PM UTC 24 Oct 09 03:58:17 PM UTC 24 264719238 ps
T371 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/5.spi_device_mailbox.3070648257 Oct 09 03:58:12 PM UTC 24 Oct 09 03:58:17 PM UTC 24 232362306 ps
T296 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/5.spi_device_pass_addr_payload_swap.113721698 Oct 09 03:58:08 PM UTC 24 Oct 09 03:58:21 PM UTC 24 10880314903 ps
T36 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_stress_all.2545899083 Oct 09 03:55:48 PM UTC 24 Oct 09 03:58:22 PM UTC 24 10431028572 ps
T166 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_all.2305649102 Oct 09 03:58:03 PM UTC 24 Oct 09 03:58:22 PM UTC 24 2998973626 ps
T167 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/5.spi_device_cfg_cmd.2224394859 Oct 09 03:58:18 PM UTC 24 Oct 09 03:58:24 PM UTC 24 474518813 ps
T168 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_mode.101825875 Oct 09 03:58:18 PM UTC 24 Oct 09 03:58:24 PM UTC 24 468814841 ps
T169 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_read_hw_reg.2730063768 Oct 09 03:58:02 PM UTC 24 Oct 09 03:58:25 PM UTC 24 3818157299 ps
T170 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_mailbox.2670726231 Oct 09 03:57:37 PM UTC 24 Oct 09 03:58:30 PM UTC 24 4919357418 ps
T171 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/5.spi_device_alert_test.318444576 Oct 09 03:58:31 PM UTC 24 Oct 09 03:58:33 PM UTC 24 13255075 ps
T145 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_and_tpm_min_idle.4086728978 Oct 09 03:56:40 PM UTC 24 Oct 09 03:58:34 PM UTC 24 18306777454 ps
T97 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/5.spi_device_read_buffer_direct.2886888488 Oct 09 03:58:23 PM UTC 24 Oct 09 03:58:34 PM UTC 24 509858474 ps
T172 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_csb_read.2130212619 Oct 09 03:58:34 PM UTC 24 Oct 09 03:58:36 PM UTC 24 31014612 ps
T372 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_mem_parity.1013702615 Oct 09 03:58:35 PM UTC 24 Oct 09 03:58:38 PM UTC 24 14601269 ps
T373 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_read_hw_reg.3272566508 Oct 09 03:58:35 PM UTC 24 Oct 09 03:58:40 PM UTC 24 514378071 ps
T354 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_rw.429090349 Oct 09 03:58:39 PM UTC 24 Oct 09 03:58:41 PM UTC 24 29514092 ps
T374 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.146816793 Oct 09 03:58:39 PM UTC 24 Oct 09 03:58:41 PM UTC 24 428537753 ps
T107 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_mode_ignore_cmds.62458938 Oct 09 03:57:45 PM UTC 24 Oct 09 03:58:42 PM UTC 24 5413121032 ps
T178 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_and_tpm_min_idle.3953057636 Oct 09 03:57:52 PM UTC 24 Oct 09 03:58:42 PM UTC 24 7382315821 ps
T223 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/5.spi_device_upload.2610481992 Oct 09 03:58:13 PM UTC 24 Oct 09 03:58:46 PM UTC 24 15265207557 ps
T375 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_cfg_cmd.3108707607 Oct 09 03:58:46 PM UTC 24 Oct 09 03:58:51 PM UTC 24 33840741 ps
T37 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/5.spi_device_stress_all.304831497 Oct 09 03:58:26 PM UTC 24 Oct 09 03:59:01 PM UTC 24 2309660638 ps
T231 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_pass_cmd_filtering.3237225243 Oct 09 03:58:42 PM UTC 24 Oct 09 03:59:02 PM UTC 24 1694947989 ps
T376 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_mode.2821510317 Oct 09 03:58:51 PM UTC 24 Oct 09 03:59:04 PM UTC 24 1941956421 ps
T351 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_all.2191355480 Oct 09 03:58:37 PM UTC 24 Oct 09 03:59:08 PM UTC 24 18611302298 ps
T280 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_intercept.1079209064 Oct 09 03:58:42 PM UTC 24 Oct 09 03:59:10 PM UTC 24 4493017682 ps
T377 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_read_buffer_direct.2002069245 Oct 09 03:59:03 PM UTC 24 Oct 09 03:59:11 PM UTC 24 261024503 ps
T378 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_alert_test.293064899 Oct 09 03:59:11 PM UTC 24 Oct 09 03:59:14 PM UTC 24 13140327 ps
T240 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_pass_addr_payload_swap.4144130344 Oct 09 03:58:42 PM UTC 24 Oct 09 03:59:16 PM UTC 24 76485113574 ps
T379 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_csb_read.238356075 Oct 09 03:59:14 PM UTC 24 Oct 09 03:59:17 PM UTC 24 274653105 ps
T380 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.3287257460 Oct 09 03:59:17 PM UTC 24 Oct 09 03:59:20 PM UTC 24 19706416 ps
T381 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mem_parity.1977117361 Oct 09 03:59:17 PM UTC 24 Oct 09 03:59:20 PM UTC 24 15529396 ps
T59 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_all.1866073525 Oct 09 03:55:44 PM UTC 24 Oct 09 03:59:21 PM UTC 24 34991707198 ps
T382 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_all.2513268032 Oct 09 03:59:21 PM UTC 24 Oct 09 03:59:23 PM UTC 24 23403734 ps
T383 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.1343753080 Oct 09 03:59:21 PM UTC 24 Oct 09 03:59:23 PM UTC 24 26823156 ps
T384 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_rw.15019582 Oct 09 03:59:22 PM UTC 24 Oct 09 03:59:25 PM UTC 24 756654031 ps
T58 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.3976870842 Oct 09 03:59:22 PM UTC 24 Oct 09 03:59:29 PM UTC 24 989056670 ps
T294 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.3105777342 Oct 09 03:59:24 PM UTC 24 Oct 09 03:59:29 PM UTC 24 493712338 ps
T200 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_upload.501021235 Oct 09 03:58:43 PM UTC 24 Oct 09 03:59:31 PM UTC 24 17092497889 ps
T181 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_all.2505288372 Oct 09 03:59:05 PM UTC 24 Oct 09 03:59:33 PM UTC 24 1085590062 ps
T252 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_upload.2304127487 Oct 09 03:59:30 PM UTC 24 Oct 09 03:59:34 PM UTC 24 151363476 ps
T385 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode_ignore_cmds.2117034002 Oct 09 03:59:34 PM UTC 24 Oct 09 03:59:36 PM UTC 24 12977999 ps
T265 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_cfg_cmd.1813410022 Oct 09 03:59:30 PM UTC 24 Oct 09 03:59:38 PM UTC 24 168175936 ps
T386 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.277287902 Oct 09 03:59:35 PM UTC 24 Oct 09 03:59:42 PM UTC 24 1466534990 ps
T387 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode.698648407 Oct 09 03:59:32 PM UTC 24 Oct 09 03:59:45 PM UTC 24 556090860 ps
T235 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_intercept.2304175531 Oct 09 03:59:24 PM UTC 24 Oct 09 03:59:46 PM UTC 24 3218371159 ps
T90 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.4168719329 Oct 09 03:55:46 PM UTC 24 Oct 09 03:59:46 PM UTC 24 24707030440 ps
T388 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_alert_test.1006733628 Oct 09 03:59:46 PM UTC 24 Oct 09 03:59:48 PM UTC 24 99512242 ps
T389 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_csb_read.124743128 Oct 09 03:59:47 PM UTC 24 Oct 09 03:59:49 PM UTC 24 54135117 ps
T390 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mem_parity.592440658 Oct 09 03:59:47 PM UTC 24 Oct 09 03:59:49 PM UTC 24 23996070 ps
T206 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_and_tpm.3949156091 Oct 09 03:58:25 PM UTC 24 Oct 09 03:59:52 PM UTC 24 26737721293 ps
T391 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_sts_read.3694924587 Oct 09 03:59:50 PM UTC 24 Oct 09 03:59:52 PM UTC 24 29001744 ps
T182 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_and_tpm.1549176408 Oct 09 03:59:07 PM UTC 24 Oct 09 03:59:53 PM UTC 24 23836823228 ps
T392 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.725112337 Oct 09 03:59:49 PM UTC 24 Oct 09 03:59:54 PM UTC 24 1002285105 ps
T247 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm.1912643143 Oct 09 03:59:38 PM UTC 24 Oct 09 03:59:57 PM UTC 24 717126904 ps
T352 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_rw.51879791 Oct 09 03:59:52 PM UTC 24 Oct 09 03:59:59 PM UTC 24 3098763329 ps
T279 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_intercept.2034667748 Oct 09 03:59:56 PM UTC 24 Oct 09 04:00:03 PM UTC 24 160762810 ps
T270 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.3215309422 Oct 09 03:59:53 PM UTC 24 Oct 09 04:00:09 PM UTC 24 6975415699 ps
T215 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_and_tpm_min_idle.1360428426 Oct 09 03:59:08 PM UTC 24 Oct 09 04:00:10 PM UTC 24 7558506040 ps
T98 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_mode_ignore_cmds.3641251126 Oct 09 03:55:31 PM UTC 24 Oct 09 04:00:12 PM UTC 24 49141657097 ps
T300 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_cfg_cmd.1633673782 Oct 09 04:00:08 PM UTC 24 Oct 09 04:00:12 PM UTC 24 197200971 ps
T38 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_stress_all.4273190678 Oct 09 03:59:11 PM UTC 24 Oct 09 04:00:20 PM UTC 24 3071380257 ps
T60 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_mode_ignore_cmds.3749435729 Oct 09 03:54:51 PM UTC 24 Oct 09 04:00:24 PM UTC 24 84143950620 ps
T393 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.1142446050 Oct 09 04:00:12 PM UTC 24 Oct 09 04:00:24 PM UTC 24 1435814629 ps
T48 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_and_tpm.2171640991 Oct 09 03:57:52 PM UTC 24 Oct 09 04:00:24 PM UTC 24 9622168322 ps
T394 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mailbox.4192523383 Oct 09 03:59:58 PM UTC 24 Oct 09 04:00:26 PM UTC 24 9442871300 ps
T214 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_upload.1860303313 Oct 09 04:00:00 PM UTC 24 Oct 09 04:00:28 PM UTC 24 15307690266 ps
T395 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_alert_test.644915437 Oct 09 04:00:25 PM UTC 24 Oct 09 04:00:28 PM UTC 24 73067946 ps
T396 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_csb_read.2118969038 Oct 09 04:00:27 PM UTC 24 Oct 09 04:00:29 PM UTC 24 17700374 ps
T61 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.222924052 Oct 09 03:59:54 PM UTC 24 Oct 09 04:00:30 PM UTC 24 12891427548 ps
T397 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mem_parity.1097914213 Oct 09 04:00:28 PM UTC 24 Oct 09 04:00:31 PM UTC 24 86056845 ps
T398 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.54115675 Oct 09 04:00:32 PM UTC 24 Oct 09 04:00:34 PM UTC 24 94442164 ps
T399 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_rw.2804543471 Oct 09 04:00:32 PM UTC 24 Oct 09 04:00:35 PM UTC 24 49012715 ps
T275 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mailbox.5735935 Oct 09 03:59:26 PM UTC 24 Oct 09 04:00:39 PM UTC 24 14894982929 ps
T278 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_intercept.1095866254 Oct 09 04:00:36 PM UTC 24 Oct 09 04:00:44 PM UTC 24 300990996 ps
T62 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.1035787076 Oct 09 03:59:39 PM UTC 24 Oct 09 04:00:45 PM UTC 24 7457002408 ps
T286 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.356838000 Oct 09 04:00:35 PM UTC 24 Oct 09 04:00:49 PM UTC 24 1580462367 ps
T224 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_mode_ignore_cmds.1154987931 Oct 09 03:59:01 PM UTC 24 Oct 09 04:00:50 PM UTC 24 57684333665 ps
T261 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_cfg_cmd.1460783382 Oct 09 04:00:47 PM UTC 24 Oct 09 04:00:51 PM UTC 24 58460480 ps
T250 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode.2050359194 Oct 09 04:00:09 PM UTC 24 Oct 09 04:00:51 PM UTC 24 1503546767 ps
T343 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_all.1534311636 Oct 09 04:00:31 PM UTC 24 Oct 09 04:00:53 PM UTC 24 19769949477 ps
T400 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.3920687842 Oct 09 04:00:28 PM UTC 24 Oct 09 04:00:56 PM UTC 24 8225774688 ps
T262 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_upload.360028977 Oct 09 04:00:45 PM UTC 24 Oct 09 04:00:57 PM UTC 24 867135939 ps
T350 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_all.3281427922 Oct 09 03:59:50 PM UTC 24 Oct 09 04:00:57 PM UTC 24 52698454981 ps
T401 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.858520638 Oct 09 04:00:52 PM UTC 24 Oct 09 04:00:59 PM UTC 24 810338679 ps
T402 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_alert_test.3120677781 Oct 09 04:00:57 PM UTC 24 Oct 09 04:01:00 PM UTC 24 10943321 ps
T255 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.1841350878 Oct 09 04:00:32 PM UTC 24 Oct 09 04:01:01 PM UTC 24 19432204327 ps
T403 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_csb_read.927531095 Oct 09 04:01:00 PM UTC 24 Oct 09 04:01:02 PM UTC 24 26082135 ps
T404 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_mem_parity.4264237039 Oct 09 04:01:01 PM UTC 24 Oct 09 04:01:03 PM UTC 24 32659180 ps
T405 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_sts_read.2185967665 Oct 09 04:01:04 PM UTC 24 Oct 09 04:01:06 PM UTC 24 68863848 ps
T334 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode.374100141 Oct 09 04:00:51 PM UTC 24 Oct 09 04:01:07 PM UTC 24 3072203295 ps
T406 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_rw.1175822336 Oct 09 04:01:07 PM UTC 24 Oct 09 04:01:10 PM UTC 24 112379498 ps
T349 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_all.4065563064 Oct 09 04:01:03 PM UTC 24 Oct 09 04:01:13 PM UTC 24 1528164838 ps
T269 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_mailbox.3178617538 Oct 09 03:58:43 PM UTC 24 Oct 09 04:01:16 PM UTC 24 58270714252 ps
T407 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_read_hw_reg.163233601 Oct 09 04:01:02 PM UTC 24 Oct 09 04:01:19 PM UTC 24 11929095185 ps
T237 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_pass_addr_payload_swap.4123504204 Oct 09 04:01:11 PM UTC 24 Oct 09 04:01:21 PM UTC 24 8794224067 ps
T256 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_pass_cmd_filtering.2795002377 Oct 09 04:01:07 PM UTC 24 Oct 09 04:01:21 PM UTC 24 535510515 ps
T274 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_intercept.2607579992 Oct 09 04:01:14 PM UTC 24 Oct 09 04:01:24 PM UTC 24 213775890 ps
T249 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_upload.1884300737 Oct 09 04:01:19 PM UTC 24 Oct 09 04:01:31 PM UTC 24 6965054408 ps
T266 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_cfg_cmd.3053205034 Oct 09 04:01:20 PM UTC 24 Oct 09 04:01:32 PM UTC 24 1045181239 ps
T85 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_mode_ignore_cmds.3634731313 Oct 09 03:58:22 PM UTC 24 Oct 09 04:01:33 PM UTC 24 98674846890 ps
T408 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_alert_test.3808630884 Oct 09 04:01:34 PM UTC 24 Oct 09 04:01:36 PM UTC 24 22592693 ps
T86 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_all.914865416 Oct 09 03:58:23 PM UTC 24 Oct 09 04:01:37 PM UTC 24 26158628911 ps
T409 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_csb_read.2741595426 Oct 09 04:01:37 PM UTC 24 Oct 09 04:01:39 PM UTC 24 13021662 ps
T410 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mailbox.2344338262 Oct 09 04:00:40 PM UTC 24 Oct 09 04:01:40 PM UTC 24 4474733534 ps
T411 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_mem_parity.267289663 Oct 09 04:01:38 PM UTC 24 Oct 09 04:01:40 PM UTC 24 33903216 ps
T228 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.247149701 Oct 09 04:00:51 PM UTC 24 Oct 09 04:01:41 PM UTC 24 22073420727 ps
T412 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_read_buffer_direct.1101546727 Oct 09 04:01:24 PM UTC 24 Oct 09 04:01:42 PM UTC 24 3788905022 ps
T413 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_sts_read.2895619766 Oct 09 04:01:41 PM UTC 24 Oct 09 04:01:44 PM UTC 24 54282433 ps
T414 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_read_hw_reg.3374925155 Oct 09 04:01:40 PM UTC 24 Oct 09 04:01:44 PM UTC 24 357597165 ps
T203 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_mailbox.1264489147 Oct 09 04:01:16 PM UTC 24 Oct 09 04:01:45 PM UTC 24 1872511500 ps
T348 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_and_tpm.3112030050 Oct 09 04:01:30 PM UTC 24 Oct 09 04:01:46 PM UTC 24 28932728425 ps
T415 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_pass_cmd_filtering.1215675905 Oct 09 04:01:43 PM UTC 24 Oct 09 04:01:46 PM UTC 24 160437457 ps
T416 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_rw.359798616 Oct 09 04:01:42 PM UTC 24 Oct 09 04:01:48 PM UTC 24 160591097 ps
T417 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_pass_addr_payload_swap.3711118155 Oct 09 04:01:45 PM UTC 24 Oct 09 04:01:49 PM UTC 24 75421034 ps
T418 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_mailbox.1034716324 Oct 09 04:01:46 PM UTC 24 Oct 09 04:01:50 PM UTC 24 29728629 ps
T272 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_cfg_cmd.57869472 Oct 09 04:01:47 PM UTC 24 Oct 09 04:01:52 PM UTC 24 238155656 ps
T353 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_all.1521000557 Oct 09 04:01:41 PM UTC 24 Oct 09 04:01:56 PM UTC 24 2357449157 ps
T238 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_upload.2062434826 Oct 09 04:01:47 PM UTC 24 Oct 09 04:01:58 PM UTC 24 1876871021 ps
T419 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_read_buffer_direct.621730080 Oct 09 04:01:51 PM UTC 24 Oct 09 04:02:00 PM UTC 24 427240881 ps
T257 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_intercept.2517034393 Oct 09 04:01:45 PM UTC 24 Oct 09 04:02:02 PM UTC 24 2845506135 ps
T336 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_mode.3281667787 Oct 09 04:01:49 PM UTC 24 Oct 09 04:02:02 PM UTC 24 471206358 ps
T358 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_and_tpm_min_idle.1025347556 Oct 09 04:01:32 PM UTC 24 Oct 09 04:02:02 PM UTC 24 3200987366 ps
T420 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_alert_test.3328584714 Oct 09 04:02:01 PM UTC 24 Oct 09 04:02:03 PM UTC 24 55580299 ps
T421 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_read_hw_reg.4021669869 Oct 09 04:02:03 PM UTC 24 Oct 09 04:02:05 PM UTC 24 11789557 ps
T422 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/12.spi_device_csb_read.76562298 Oct 09 04:02:03 PM UTC 24 Oct 09 04:02:05 PM UTC 24 55439331 ps
T423 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/12.spi_device_mem_parity.1097616505 Oct 09 04:02:03 PM UTC 24 Oct 09 04:02:06 PM UTC 24 121239522 ps
T424 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_sts_read.2490476350 Oct 09 04:02:07 PM UTC 24 Oct 09 04:02:09 PM UTC 24 118746642 ps
T425 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_rw.440769344 Oct 09 04:02:07 PM UTC 24 Oct 09 04:02:09 PM UTC 24 41218211 ps
T426 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_mode.1930065688 Oct 09 04:01:22 PM UTC 24 Oct 09 04:02:11 PM UTC 24 2294069170 ps
T277 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/12.spi_device_pass_cmd_filtering.1545052469 Oct 09 04:02:07 PM UTC 24 Oct 09 04:02:15 PM UTC 24 1194516040 ps
T180 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_all.462315329 Oct 09 04:00:14 PM UTC 24 Oct 09 04:02:17 PM UTC 24 31302890576 ps
T99 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/12.spi_device_intercept.3150753758 Oct 09 04:02:11 PM UTC 24 Oct 09 04:02:18 PM UTC 24 457703238 ps
T427 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/12.spi_device_pass_addr_payload_swap.2879960101 Oct 09 04:02:10 PM UTC 24 Oct 09 04:02:18 PM UTC 24 255896273 ps
T276 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/12.spi_device_upload.3770796640 Oct 09 04:02:16 PM UTC 24 Oct 09 04:02:21 PM UTC 24 2070371693 ps
T306 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/12.spi_device_cfg_cmd.2646601688 Oct 09 04:02:17 PM UTC 24 Oct 09 04:02:26 PM UTC 24 2186729645 ps
T254 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_mode.58549682 Oct 09 04:02:18 PM UTC 24 Oct 09 04:02:26 PM UTC 24 163508527 ps
T216 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_and_tpm.342589645 Oct 09 04:00:54 PM UTC 24 Oct 09 04:02:26 PM UTC 24 9310996368 ps
T100 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_mode_ignore_cmds.2461403369 Oct 09 04:01:22 PM UTC 24 Oct 09 04:02:35 PM UTC 24 12507798154 ps
T347 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_all.815689334 Oct 09 04:02:04 PM UTC 24 Oct 09 04:02:36 PM UTC 24 3662749815 ps
T428 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/12.spi_device_alert_test.1345055924 Oct 09 04:02:37 PM UTC 24 Oct 09 04:02:39 PM UTC 24 37897287 ps
T429 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/13.spi_device_csb_read.607221104 Oct 09 04:02:40 PM UTC 24 Oct 09 04:02:43 PM UTC 24 17595984 ps
T177 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_and_tpm_min_idle.896146060 Oct 09 03:55:05 PM UTC 24 Oct 09 04:02:44 PM UTC 24 191829257255 ps
T179 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_all.1624895317 Oct 09 04:01:52 PM UTC 24 Oct 09 04:02:44 PM UTC 24 5294167241 ps
T210 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.2694328048 Oct 09 04:00:11 PM UTC 24 Oct 09 04:02:45 PM UTC 24 14576710255 ps
T430 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/13.spi_device_mem_parity.1063861816 Oct 09 04:02:43 PM UTC 24 Oct 09 04:02:46 PM UTC 24 40775246 ps
T431 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_sts_read.3754501094 Oct 09 04:02:46 PM UTC 24 Oct 09 04:02:48 PM UTC 24 103481727 ps
T432 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_rw.1231846673 Oct 09 04:02:47 PM UTC 24 Oct 09 04:02:50 PM UTC 24 61873225 ps
T433 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/12.spi_device_read_buffer_direct.1265356881 Oct 09 04:02:23 PM UTC 24 Oct 09 04:02:51 PM UTC 24 8460292147 ps
T434 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/13.spi_device_pass_cmd_filtering.1565235935 Oct 09 04:02:49 PM UTC 24 Oct 09 04:02:54 PM UTC 24 57158004 ps
T435 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/13.spi_device_intercept.3509509645 Oct 09 04:02:51 PM UTC 24 Oct 09 04:02:58 PM UTC 24 274392752 ps
T39 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_stress_all.1375494061 Oct 09 03:54:12 PM UTC 24 Oct 09 04:03:02 PM UTC 24 50456068744 ps
T436 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_read_hw_reg.1799441247 Oct 09 04:02:45 PM UTC 24 Oct 09 04:03:02 PM UTC 24 4289455031 ps
T234 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_all.1460667608 Oct 09 03:59:37 PM UTC 24 Oct 09 04:03:08 PM UTC 24 31077035012 ps
T301 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/13.spi_device_pass_addr_payload_swap.3579967906 Oct 09 04:02:51 PM UTC 24 Oct 09 04:03:08 PM UTC 24 4908824033 ps