Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	33847	1			T7	2		T13	4		T19	36
auto[SpiFlashAddrCfg]	7449	1			T7	4		T8	2		T19	3
auto[SpiFlashAddr3b]	8997	1			T7	6		T13	4		T17	2
auto[SpiFlashAddr4b]	7704	1			T7	2		T8	2		T9	2

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32923

1

T7

14

T9

2

T12

1

auto[1]

25074

1

T8

4

T17

2

T19

27

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30631

1

T7

6

T8

2

T9

2

auto[1]

27366

1

T7

8

T8

2

T13

8

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	38322	1			T7	8		T8	4		T13	6
values[1]	1142	1			T7	2		T32	6		T54	9
values[2]	1375	1			T45	1		T32	2		T54	1
values[3]	1514	1			T13	6		T32	5		T54	7
values[4]	1468	1			T19	3		T51	2		T30	1
values[5]	1318	1			T19	7		T30	3		T32	2
values[6]	1521	1			T12	1		T30	1		T54	4
values[7]	1486	1			T56	6		T32	1		T54	6
values[8]	9851	1			T7	4		T9	2		T13	8

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32544

1

T7

14

T8

4

T9

2

auto[1]

25453

1

T12

1

T19

56

T45

5

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

54809

1

T7

12

T9

2

T12

1

write

3188

1

T7

2

T8

4

T13

4

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

18843

1

T7

4

T9

2

T12

1

valids[0x1]

39154

1

T7

10

T8

4

T13

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1458	1			T19	2		T30	1		T32	2
internal_process_ops[0x5a]	1487	1			T51	2		T32	2		T54	5
internal_process_ops[0x05]	20413	1			T19	17		T56	2		T30	1
internal_process_ops[0x35]	1563	1			T19	2		T32	4		T103	2
internal_process_ops[0x15]	1556	1			T7	2		T19	1		T51	2
internal_process_ops[0x03]	1101	1			T32	1		T53	2		T54	5
internal_process_ops[0x0b]	1101	1			T7	2		T13	2		T30	1
internal_process_ops[0x3b]	1135	1			T9	2		T45	1		T53	4
internal_process_ops[0x6b]	1117	1			T12	1		T13	6		T45	3
internal_process_ops[0xbb]	1035	1			T13	4		T45	1		T30	1
internal_process_ops[0xeb]	1057	1			T32	2		T53	4		T54	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56401

1

T7

14

T9

2

T12

1

auto[1]

1596

1

T8

4

T19

2

T32

9

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

55781

1

T7

14

T8

4

T9

2

auto[1]

2216

1

T19

2

T32

6

T54

16

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10880

1

T7

2

T13

2

T55

2

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7076

1

T30

1

T54

8

T46

123

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2092

1

T7

2

T56

6

T30

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1902

1

T54

15

T46

18

T47

12

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2554

1

T7

6

T13

2

T51

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2317

1

T17

2

T30

3

T54

15

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2126

1

T7

2

T9

2

T13

12

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1964

1

T30

4

T54

12

T175

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

113

1

T13

2

T56

2

T36

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

90

1

T54

2

T46

1

T47

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

93

1

T36

3

T107

3

T86

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

128

1

T59

2

T60

1

T61

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

106

1

T7

2

T176

2

T47

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

101

1

T54

1

T46

1

T47

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

91

1

T59

1

T86

2

T177

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

95

1

T8

2

T54

1

T59

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

96

1

T13

2

T46

4

T36

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

88

1

T46

2

T60

1

T86

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

107

1

T54

2

T46

4

T47

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

90

1

T46

1

T36

1

T107

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

139

1

T46

4

T59

1

T60

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

95

1

T54

5

T46

2

T47

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

84

1

T54

3

T47

5

T107

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

117

1

T8

2

T54

1

T46

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9151

1

T19

15

T32

57

T49

184

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5905

1

T19

21

T32

8

T49

118

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1331

1

T19

1

T32

7

T153

5

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1340

1

T32

9

T49

19

T50

11

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1715

1

T19

3

T45

4

T32

4

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1662

1

T19

3

T32

11

T49

12

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1484

1

T12

1

T19

9

T45

1

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1310

1

T32

3

T49

6

T50

13

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

101

1

T50

2

T145

1

T178

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

111

1

T32

2

T145

3

T179

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

112

1

T50

1

T81

7

T23

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

87

1

T32

1

T50

3

T81

6

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

74

1

T19

1

T50

1

T145

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

92

1

T49

3

T81

1

T90

5

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

111

1

T49

2

T81

2

T23

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

114

1

T19

1

T49

2

T81

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

84

1

T49

1

T50

2

T180

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

103

1

T49

1

T50

1

T81

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

98

1

T19

1

T49

1

T50

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

83

1

T32

6

T81

2

T23

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

93

1

T49

1

T98

3

T38

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

104

1

T49

3

T23

1

T145

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

90

1

T181

2

T90

4

T182

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

98

1

T19

1

T49

7

T23

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3790	1			T7	4		T13	2		T55	2
auto[0]	values[0]	valids[0x1]	17120	1			T7	4		T8	4		T13	4
auto[0]	values[1]	valids[0x1]	629	1			T7	2		T54	9		T183	2
auto[0]	values[2]	valids[0x0]	543	1			T46	8		T47	2		T36	13
auto[0]	values[2]	valids[0x1]	311	1			T54	1		T46	2		T47	6
auto[0]	values[3]	valids[0x0]	633	1			T13	6		T54	3		T106	2
auto[0]	values[3]	valids[0x1]	323	1			T54	4		T36	1		T59	2
auto[0]	values[4]	valids[0x0]	567	1			T53	4		T54	3		T101	2
auto[0]	values[4]	valids[0x1]	302	1			T51	2		T30	1		T184	2
auto[0]	values[5]	valids[0x0]	464	1			T54	4		T46	5		T47	2
auto[0]	values[5]	valids[0x1]	314	1			T30	3		T176	2		T46	2
auto[0]	values[6]	valids[0x0]	579	1			T30	1		T54	3		T101	2
auto[0]	values[6]	valids[0x1]	267	1			T54	1		T104	4		T46	3
auto[0]	values[7]	valids[0x0]	574	1			T56	6		T54	4		T103	2
auto[0]	values[7]	valids[0x1]	328	1			T54	2		T106	2		T46	6
auto[0]	values[8]	valids[0x0]	3633	1			T9	2		T13	4		T17	2
auto[0]	values[8]	valids[0x1]	2167	1			T7	4		T13	4		T56	2
auto[1]	values[0]	valids[0x0]	3571	1			T19	11		T32	8		T49	47
auto[1]	values[0]	valids[0x1]	13841	1			T19	28		T32	65		T49	285
auto[1]	values[1]	valids[0x1]	513	1			T32	6		T49	1		T50	3
auto[1]	values[2]	valids[0x0]	326	1			T45	1		T32	2		T49	2
auto[1]	values[2]	valids[0x1]	195	1			T49	1		T50	4		T23	2
auto[1]	values[3]	valids[0x0]	321	1			T32	2		T49	3		T50	6
auto[1]	values[3]	valids[0x1]	237	1			T32	3		T153	2		T49	4
auto[1]	values[4]	valids[0x0]	340	1			T19	2		T32	3		T49	3
auto[1]	values[4]	valids[0x1]	259	1			T19	1		T49	4		T50	2
auto[1]	values[5]	valids[0x0]	308	1			T19	5		T32	2		T49	2
auto[1]	values[5]	valids[0x1]	232	1			T19	2		T49	3		T50	1
auto[1]	values[6]	valids[0x0]	408	1			T12	1		T49	6		T50	2
auto[1]	values[6]	valids[0x1]	267	1			T49	3		T81	2		T23	2
auto[1]	values[7]	valids[0x0]	356	1			T32	1		T102	2		T49	2
auto[1]	values[7]	valids[0x1]	228	1			T49	1		T50	2		T81	2
auto[1]	values[8]	valids[0x0]	2430	1			T19	6		T45	4		T32	20
auto[1]	values[8]	valids[0x1]	1621	1			T19	1		T32	7		T153	1