Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3311004

1

T7

1

T8

1

T9

1092

auto[1]

31232

1

T19

16

T32

39

T54

616

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

951418

1

T7

1

T8

1

T9

1092

auto[1]

2390818

1

T19

3944

T51

2

T56

6

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	692283	1			T7	1		T8	1		T9	965
auto[524288:1048575]	413911	1			T9	2		T11	2		T55	578
auto[1048576:1572863]	354061	1			T9	1		T12	231		T19	2
auto[1572864:2097151]	358479	1			T11	36		T19	2		T51	430
auto[2097152:2621439]	406743	1			T9	124		T18	1		T19	1
auto[2621440:3145727]	313434	1			T11	37		T19	1		T51	934
auto[3145728:3670015]	406470	1			T11	46		T12	99		T19	3698
auto[3670016:4194303]	396855	1			T18	8		T19	257		T51	1806

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2423903

1

T7

1

T8

1

T9

5

auto[1]

918333

1

T9

1087

T11

159

T12

327

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2905204

1

T7

1

T8

1

T9

1092

auto[1]

437032

1

T19

1

T55

582

T32

2

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	219951	1			T7	1		T8	1		T9	965
auto[0]	auto[0]	auto[0:524287]	auto[1]	404507	1			T51	2		T56	6		T32	257
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	128538	1			T9	2		T11	2		T51	6240
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	234855	1			T32	516		T49	768		T50	2
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	74880	1			T9	1		T12	231		T19	2
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	223163	1			T30	256		T32	2645		T54	108
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	80771	1			T11	36		T19	2		T51	430
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	218090	1			T32	3244		T54	256		T222	11
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	123242	1			T9	124		T18	1		T19	1
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	226808	1			T222	1		T104	2		T49	640
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	56321	1			T11	37		T19	1		T51	934
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	209074	1			T222	2601		T104	255		T49	512
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	113239	1			T11	46		T12	99		T19	7
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	229886	1			T19	3674		T54	1801		T222	1043
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	138197	1			T18	8		T19	1		T51	1806
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	197769	1			T19	256		T30	128		T32	130
auto[0]	auto[1]	auto[0:524287]	auto[0]	1252	1			T55	2		T54	17		T49	1
auto[0]	auto[1]	auto[0:524287]	auto[1]	62473	1			T49	162		T81	261		T23	1284
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	2634	1			T55	578		T49	2		T50	1
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	44965	1			T49	1		T50	769		T23	430
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	508	1			T54	7		T49	7		T81	44
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	50819	1			T49	2563		T81	2227		T46	2
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	1342	1			T32	2		T54	37		T81	67
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	54269	1			T54	3009		T49	256		T50	256
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	765	1			T49	4		T50	4		T81	11
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	51344	1			T49	643		T50	957		T81	256
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	3969	1			T54	2		T50	3		T81	18
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	41382	1			T50	591		T59	1		T38	512
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	910	1			T19	1		T55	2		T54	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	58998	1			T23	256		T36	2759		T107	513
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	1108	1			T50	4		T81	12		T46	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	54975	1			T50	519		T81	256		T46	256
auto[1]	auto[0]	auto[0:524287]	auto[0]	466	1			T32	1		T54	3		T49	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	2973	1			T32	1		T49	27		T46	6
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	328	1			T32	1		T23	3		T46	2
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1959	1			T32	7		T23	120		T46	20
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	420	1			T32	1		T54	6		T49	2
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	3817	1			T32	5		T49	85		T46	5
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	390	1			T32	1		T49	1		T46	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2925	1			T32	8		T49	15		T46	3
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	376	1			T50	3		T81	19		T46	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	3408	1			T50	8		T81	5		T47	11
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	367	1			T54	15		T50	2		T81	11
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1950	1			T50	1		T23	7		T46	37
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	374	1			T19	2		T54	6		T50	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1931	1			T19	14		T50	2		T46	47
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	355	1			T32	2		T54	12		T49	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	3874	1			T32	12		T54	555		T49	8
auto[1]	auto[1]	auto[0:524287]	auto[0]	101	1			T23	2		T46	1		T36	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	560	1			T23	13		T46	3		T36	1
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	76	1			T49	1		T81	2		T47	3
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	556	1			T49	40		T47	22		T36	19
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	69	1			T49	2		T81	8		T46	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	385	1			T49	28		T46	20		T47	38
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	107	1			T54	19		T81	8		T36	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	585	1			T36	6		T182	1		T86	7
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	128	1			T81	7		T145	1		T206	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	672	1			T145	3		T206	2		T38	2
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	44	1			T50	1		T81	3		T59	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	327	1			T50	1		T59	8		T39	9
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	89	1			T36	1		T107	3		T48	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	1043	1			T36	69		T107	599		T48	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	101	1			T50	1		T181	1		T90	2
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	476	1			T181	26		T90	1		T62	29

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1969387	1			T7	1		T8	1		T9	5
auto[0]	auto[0]	auto[1]	909904	1			T9	1087		T11	159		T12	327
auto[0]	auto[1]	auto[0]	423935	1			T19	1		T55	5		T32	2
auto[0]	auto[1]	auto[1]	7778	1			T55	577		T49	1		T259	1
auto[1]	auto[0]	auto[0]	25379	1			T19	14		T32	39		T54	592
auto[1]	auto[0]	auto[1]	534	1			T19	2		T54	5		T81	5
auto[1]	auto[1]	auto[0]	5202	1			T54	17		T49	71		T50	3
auto[1]	auto[1]	auto[1]	117	1			T54	2		T81	6		T47	2