Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2276194	1			T1	1		T2	1		T4	1
all_pins[1]	2276194	1			T1	1		T2	1		T4	1
all_pins[2]	2276194	1			T1	1		T2	1		T4	1
all_pins[3]	2276194	1			T1	1		T2	1		T4	1
all_pins[4]	2276194	1			T1	1		T2	1		T4	1
all_pins[5]	2276194	1			T1	1		T2	1		T4	1
all_pins[6]	2276194	1			T1	1		T2	1		T4	1
all_pins[7]	2276194	1			T1	1		T2	1		T4	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	18186729	1			T1	8		T2	8		T4	8
values[0x1]	22823	1			T36	8		T37	22		T38	1406
transitions[0x0=>0x1]	21793	1			T36	5		T37	16		T38	1160
transitions[0x1=>0x0]	21808	1			T36	5		T37	16		T38	1161

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2275319	1			T1	1		T2	1		T4	1
all_pins[0]	values[0x1]	875	1			T37	6		T38	41		T39	3
all_pins[0]	transitions[0x0=>0x1]	680	1			T37	2		T38	22		T39	2
all_pins[0]	transitions[0x1=>0x0]	173	1			T37	3		T38	7		T39	2
all_pins[1]	values[0x0]	2275826	1			T1	1		T2	1		T4	1
all_pins[1]	values[0x1]	368	1			T37	7		T38	26		T39	3
all_pins[1]	transitions[0x0=>0x1]	283	1			T37	7		T38	23		T39	3
all_pins[1]	transitions[0x1=>0x0]	208	1			T36	1		T38	1		T39	4
all_pins[2]	values[0x0]	2275901	1			T1	1		T2	1		T4	1
all_pins[2]	values[0x1]	293	1			T36	1		T38	4		T39	4
all_pins[2]	transitions[0x0=>0x1]	236	1			T38	2		T39	2		T174	8
all_pins[2]	transitions[0x1=>0x0]	159	1			T38	1		T39	2		T160	2
all_pins[3]	values[0x0]	2275978	1			T1	1		T2	1		T4	1
all_pins[3]	values[0x1]	216	1			T36	1		T38	3		T39	4
all_pins[3]	transitions[0x0=>0x1]	161	1			T36	1		T39	4		T160	2
all_pins[3]	transitions[0x1=>0x0]	154	1			T37	1		T38	3		T39	2
all_pins[4]	values[0x0]	2275985	1			T1	1		T2	1		T4	1
all_pins[4]	values[0x1]	209	1			T37	1		T38	6		T39	2
all_pins[4]	transitions[0x0=>0x1]	162	1			T37	1		T38	5		T39	2
all_pins[4]	transitions[0x1=>0x0]	1444	1			T36	2		T37	2		T38	218
all_pins[5]	values[0x0]	2274703	1			T1	1		T2	1		T4	1
all_pins[5]	values[0x1]	1491	1			T36	2		T37	2		T38	219
all_pins[5]	transitions[0x0=>0x1]	1017	1			T36	1		T37	2		T38	4
all_pins[5]	transitions[0x1=>0x0]	18694	1			T36	2		T37	2		T38	889
all_pins[6]	values[0x0]	2257026	1			T1	1		T2	1		T4	1
all_pins[6]	values[0x1]	19168	1			T36	3		T37	2		T38	1104
all_pins[6]	transitions[0x0=>0x1]	19112	1			T36	2		T37	2		T38	1102
all_pins[6]	transitions[0x1=>0x0]	147	1			T37	4		T38	1		T39	3
all_pins[7]	values[0x0]	2275991	1			T1	1		T2	1		T4	1
all_pins[7]	values[0x1]	203	1			T36	1		T37	4		T38	3
all_pins[7]	transitions[0x0=>0x1]	142	1			T36	1		T37	2		T38	2
all_pins[7]	transitions[0x1=>0x0]	829	1			T37	4		T38	41		T39	2