Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18480

1

T7

14

T9

2

T13

20

auto[1]

14064

1

T8

4

T17

2

T30

8

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4155	1			T55	2		T54	20		T104	8
values[1]	3531	1			T30	20		T54	20		T183	6
values[2]	4354	1			T51	4		T53	14		T125	6
values[3]	3635	1			T7	14		T9	2		T54	40
values[4]	4035	1			T17	2		T56	16		T222	10
values[5]	4343	1			T57	4		T260	2		T259	2
values[6]	4157	1			T8	4		T54	20		T103	16
values[7]	4334	1			T13	20		T54	20		T46	100

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4545	1			T55	2		T125	6		T227	10
values[1]	4139	1			T7	14		T54	20		T105	10
values[2]	3534	1			T54	40		T183	6		T260	2
values[3]	4141	1			T53	14		T54	20		T103	16
values[4]	4539	1			T9	2		T56	16		T101	16
values[5]	3684	1			T8	4		T13	20		T47	72
values[6]	4238	1			T17	2		T54	20		T57	4
values[7]	3724	1			T51	4		T30	20		T54	40

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	326	1			T55	2		T36	8		T167	4
auto[0]	values[0]	values[1]	248	1			T86	14		T210	17		T198	14
auto[0]	values[0]	values[2]	326	1			T54	10		T261	4		T204	10
auto[0]	values[0]	values[3]	310	1			T60	12		T262	16		T263	14
auto[0]	values[0]	values[4]	393	1			T104	8		T58	14		T86	36
auto[0]	values[0]	values[5]	217	1			T36	10		T59	17		T252	4
auto[0]	values[0]	values[6]	321	1			T46	14		T60	11		T207	45
auto[0]	values[0]	values[7]	291	1			T59	13		T204	15		T208	17
auto[0]	values[1]	values[0]	158	1			T46	10		T87	17		T213	39
auto[0]	values[1]	values[1]	363	1			T54	9		T105	10		T225	8
auto[0]	values[1]	values[2]	254	1			T183	6		T39	4		T264	10
auto[0]	values[1]	values[3]	321	1			T184	6		T265	8		T266	6
auto[0]	values[1]	values[4]	253	1			T86	11		T207	14		T87	10
auto[0]	values[1]	values[5]	209	1			T267	2		T248	15		T213	13
auto[0]	values[1]	values[6]	311	1			T107	8		T39	4		T207	49
auto[0]	values[1]	values[7]	282	1			T30	12		T208	9		T226	13
auto[0]	values[2]	values[0]	419	1			T125	6		T46	8		T48	12
auto[0]	values[2]	values[1]	366	1			T177	23		T251	24		T226	55
auto[0]	values[2]	values[2]	236	1			T46	30		T170	6		T244	48
auto[0]	values[2]	values[3]	366	1			T53	14		T36	9		T177	12
auto[0]	values[2]	values[4]	184	1			T176	8		T60	16		T86	15
auto[0]	values[2]	values[5]	301	1			T47	12		T36	15		T60	15
auto[0]	values[2]	values[6]	200	1			T54	15		T200	10		T268	2
auto[0]	values[2]	values[7]	272	1			T51	4		T47	36		T224	18
auto[0]	values[3]	values[0]	291	1			T46	12		T59	12		T256	18
auto[0]	values[3]	values[1]	217	1			T7	14		T36	24		T269	10
auto[0]	values[3]	values[2]	241	1			T54	11		T60	10		T210	9
auto[0]	values[3]	values[3]	281	1			T54	11		T242	51		T236	7
auto[0]	values[3]	values[4]	308	1			T9	2		T101	16		T270	6
auto[0]	values[3]	values[5]	299	1			T59	61		T210	30		T204	14
auto[0]	values[3]	values[6]	339	1			T46	38		T271	18		T87	68
auto[0]	values[3]	values[7]	238	1			T106	20		T272	2		T244	30
auto[0]	values[4]	values[0]	314	1			T210	7		T226	13		T273	26
auto[0]	values[4]	values[1]	340	1			T223	6		T99	10		T207	12
auto[0]	values[4]	values[2]	312	1			T235	6		T62	7		T210	13
auto[0]	values[4]	values[3]	287	1			T47	71		T59	9		T86	14
auto[0]	values[4]	values[4]	297	1			T56	16		T222	10		T107	11
auto[0]	values[4]	values[5]	165	1			T47	7		T207	12		T204	9
auto[0]	values[4]	values[6]	299	1			T224	9		T210	12		T253	12
auto[0]	values[4]	values[7]	244	1			T274	8		T210	15		T213	12
auto[0]	values[5]	values[0]	422	1			T48	14		T62	3		T210	11
auto[0]	values[5]	values[1]	211	1			T275	14		T86	17		T221	2
auto[0]	values[5]	values[2]	494	1			T46	27		T224	10		T276	2
auto[0]	values[5]	values[3]	216	1			T86	25		T277	8		T204	11
auto[0]	values[5]	values[4]	307	1			T46	7		T278	6		T177	14
auto[0]	values[5]	values[5]	244	1			T47	14		T207	13		T204	15
auto[0]	values[5]	values[6]	276	1			T57	4		T245	6		T36	37
auto[0]	values[5]	values[7]	322	1			T259	2		T36	84		T39	14
auto[0]	values[6]	values[0]	219	1			T227	10		T46	33		T107	7
auto[0]	values[6]	values[1]	501	1			T62	12		T242	15		T226	13
auto[0]	values[6]	values[2]	118	1			T279	2		T86	16		T207	13
auto[0]	values[6]	values[3]	360	1			T103	16		T36	33		T39	28
auto[0]	values[6]	values[4]	404	1			T280	10		T177	10		T204	36
auto[0]	values[6]	values[5]	350	1			T210	25		T219	16		T281	5
auto[0]	values[6]	values[6]	196	1			T282	18		T283	18		T239	19
auto[0]	values[6]	values[7]	222	1			T54	11		T284	20		T253	11
auto[0]	values[7]	values[0]	232	1			T36	13		T86	17		T177	11
auto[0]	values[7]	values[1]	125	1			T48	11		T204	23		T285	4
auto[0]	values[7]	values[2]	256	1			T37	8		T231	18		T206	13
auto[0]	values[7]	values[3]	324	1			T47	15		T60	31		T210	12
auto[0]	values[7]	values[4]	476	1			T249	18		T177	13		T39	14
auto[0]	values[7]	values[5]	204	1			T13	20		T107	9		T201	12
auto[0]	values[7]	values[6]	402	1			T46	14		T36	41		T226	8
auto[0]	values[7]	values[7]	200	1			T54	16		T46	13		T214	36
auto[1]	values[0]	values[0]	149	1			T36	12		T59	12		T87	7
auto[1]	values[0]	values[1]	228	1			T86	61		T210	3		T198	14
auto[1]	values[0]	values[2]	97	1			T54	10		T204	10		T219	8
auto[1]	values[0]	values[3]	150	1			T60	8		T61	24		T236	29
auto[1]	values[0]	values[4]	276	1			T86	18		T177	16		T248	41
auto[1]	values[0]	values[5]	288	1			T36	10		T59	12		T62	8
auto[1]	values[0]	values[6]	247	1			T46	48		T60	9		T207	8
auto[1]	values[0]	values[7]	288	1			T59	7		T286	22		T204	5
auto[1]	values[1]	values[0]	85	1			T46	10		T87	5		T213	12
auto[1]	values[1]	values[1]	208	1			T54	11		T225	12		T146	15
auto[1]	values[1]	values[2]	144	1			T39	17		T196	11		T248	6
auto[1]	values[1]	values[3]	168	1			T87	13		T287	11		T253	11
auto[1]	values[1]	values[4]	331	1			T86	41		T207	41		T87	10
auto[1]	values[1]	values[5]	97	1			T248	10		T213	7		T146	11
auto[1]	values[1]	values[6]	207	1			T107	12		T39	26		T207	12
auto[1]	values[1]	values[7]	140	1			T30	8		T208	13		T226	7
auto[1]	values[2]	values[0]	612	1			T46	16		T48	12		T86	119
auto[1]	values[2]	values[1]	201	1			T177	17		T226	27		T288	10
auto[1]	values[2]	values[2]	125	1			T46	8		T244	3		T289	10
auto[1]	values[2]	values[3]	190	1			T36	11		T177	11		T196	6
auto[1]	values[2]	values[4]	165	1			T60	4		T86	26		T273	6
auto[1]	values[2]	values[5]	221	1			T47	8		T36	5		T60	5
auto[1]	values[2]	values[6]	309	1			T54	5		T213	13		T41	31
auto[1]	values[2]	values[7]	187	1			T47	5		T224	22		T213	29
auto[1]	values[3]	values[0]	246	1			T46	8		T59	64		T207	23
auto[1]	values[3]	values[1]	80	1			T36	10		T86	13		T174	10
auto[1]	values[3]	values[2]	196	1			T54	9		T60	10		T210	11
auto[1]	values[3]	values[3]	258	1			T54	9		T242	4		T236	13
auto[1]	values[3]	values[4]	158	1			T210	11		T39	8		T244	23
auto[1]	values[3]	values[5]	217	1			T59	9		T210	10		T204	24
auto[1]	values[3]	values[6]	170	1			T46	12		T87	5		T89	12
auto[1]	values[3]	values[7]	96	1			T240	12		T244	8		T198	11
auto[1]	values[4]	values[0]	341	1			T210	13		T290	2		T291	18
auto[1]	values[4]	values[1]	162	1			T207	22		T208	7		T236	7
auto[1]	values[4]	values[2]	175	1			T62	43		T210	7		T292	2
auto[1]	values[4]	values[3]	272	1			T47	14		T59	32		T86	28
auto[1]	values[4]	values[4]	206	1			T107	9		T60	7		T237	20
auto[1]	values[4]	values[5]	228	1			T47	18		T207	9		T204	27
auto[1]	values[4]	values[6]	201	1			T17	2		T224	11		T210	8
auto[1]	values[4]	values[7]	192	1			T210	5		T213	9		T242	2
auto[1]	values[5]	values[0]	246	1			T48	8		T62	17		T210	9
auto[1]	values[5]	values[1]	289	1			T86	11		T253	18		T201	99
auto[1]	values[5]	values[2]	236	1			T260	2		T46	17		T224	10
auto[1]	values[5]	values[3]	230	1			T86	42		T204	9		T281	10
auto[1]	values[5]	values[4]	166	1			T46	13		T177	6		T87	19
auto[1]	values[5]	values[5]	260	1			T47	13		T207	33		T204	5
auto[1]	values[5]	values[6]	161	1			T36	19		T204	5		T293	10
auto[1]	values[5]	values[7]	263	1			T36	6		T39	16		T204	14
auto[1]	values[6]	values[0]	313	1			T46	10		T107	13		T177	33
auto[1]	values[6]	values[1]	210	1			T62	8		T242	5		T226	7
auto[1]	values[6]	values[2]	157	1			T86	10		T207	7		T219	10
auto[1]	values[6]	values[3]	206	1			T36	22		T39	13		T198	6
auto[1]	values[6]	values[4]	334	1			T175	2		T177	10		T204	7
auto[1]	values[6]	values[5]	256	1			T8	4		T210	15		T219	24
auto[1]	values[6]	values[6]	101	1			T294	2		T239	21		T295	5
auto[1]	values[6]	values[7]	210	1			T54	9		T253	9		T146	10
auto[1]	values[7]	values[0]	172	1			T36	7		T86	9		T177	10
auto[1]	values[7]	values[1]	390	1			T48	16		T204	6		T246	14
auto[1]	values[7]	values[2]	167	1			T296	2		T37	12		T206	16
auto[1]	values[7]	values[3]	202	1			T47	5		T60	9		T210	8
auto[1]	values[7]	values[4]	281	1			T177	7		T39	8		T207	2
auto[1]	values[7]	values[5]	128	1			T107	11		T201	8		T293	8
auto[1]	values[7]	values[6]	498	1			T46	60		T36	8		T226	12
auto[1]	values[7]	values[7]	277	1			T54	4		T46	13		T207	19