Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	378	1			T54	6		T57	2		T103	6
auto[ReadAddrCrossIntoMailbox]	321	1			T54	1		T46	4		T47	1
auto[ReadAddrCrossOutOfMailbox]	332	1			T54	1		T46	5		T47	1
auto[ReadAddrCrossAllMailbox]	232	1			T54	4		T46	4		T47	2
auto[ReadAddrOutsideMailbox]	3782	1			T7	2		T9	2		T13	12

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2419

1

T7

1

T9

1

T13

6

auto[1]

2626

1

T7

1

T9

1

T13

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	856	1			T53	2		T54	5		T183	2
read_ops[0x0b]	837	1			T7	2		T13	2		T30	1
read_ops[0x3b]	874	1			T9	2		T54	5		T101	2
read_ops[0x6b]	849	1			T13	6		T30	1		T53	4
read_ops[0xbb]	813	1			T13	4		T30	1		T54	8
read_ops[0xeb]	816	1			T53	4		T54	2		T101	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	26	1			T183	1		T227	1		T37	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	32	1			T54	2		T183	1		T227	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T46	1		T86	1		T177	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	32	1			T60	1		T210	1		T207	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	31	1			T206	1		T60	1		T204	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T46	1		T47	1		T36	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	22	1			T54	1		T275	2		T210	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T54	1		T275	2		T210	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	315	1			T53	1		T54	1		T105	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	327	1			T53	1		T105	1		T106	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T54	1		T57	1		T59	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	34	1			T54	1		T57	1		T177	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T59	1		T87	1		T213	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T54	1		T86	3		T177	2
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	28	1			T210	1		T207	1		T87	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	20	1			T207	1		T87	2		T213	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T54	1		T59	1		T87	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T107	1		T60	1		T86	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	293	1			T7	1		T13	1		T101	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	347	1			T7	1		T13	1		T30	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	42	1			T103	1		T60	1		T224	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	32	1			T54	1		T103	1		T107	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T59	1		T86	1		T207	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	32	1			T46	1		T204	4		T87	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	24	1			T59	1		T177	1		T39	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T60	1		T207	1		T204	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T59	1		T210	1		T253	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T59	1		T210	1		T39	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	324	1			T9	1		T101	1		T183	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	335	1			T9	1		T54	4		T101	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	37	1			T210	1		T268	1		T87	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T86	1		T210	1		T204	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T60	2		T39	1		T207	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T36	1		T86	1		T177	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T59	1		T60	1		T86	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T36	1		T86	1		T204	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T46	1		T207	1		T297	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T47	1		T297	1		T198	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	302	1			T13	3		T30	1		T53	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	349	1			T13	3		T53	2		T54	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	26	1			T103	1		T107	1		T59	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	38	1			T103	1		T274	1		T86	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T86	1		T207	1		T204	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	34	1			T48	1		T219	1		T198	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T54	1		T46	2		T177	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	37	1			T210	1		T39	2		T298	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T46	1		T47	1		T59	2
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T54	1		T299	1		T41	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	287	1			T13	2		T30	1		T54	3
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	306	1			T13	2		T54	3		T105	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	31	1			T54	1		T103	1		T86	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	25	1			T103	1		T36	2		T59	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T46	2		T87	1		T219	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	31	1			T47	1		T60	1		T224	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T46	1		T59	1		T210	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T46	1		T86	2		T204	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	28	1			T275	3		T207	1		T236	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	30	1			T46	2		T275	3		T204	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	282	1			T53	2		T101	1		T227	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	315	1			T53	2		T54	1		T101	1