Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3852	1			T30	20		T54	20		T105	10
values[1]	3931	1			T175	2		T104	8		T259	2
values[2]	4139	1			T51	4		T54	20		T103	16
values[3]	4405	1			T55	2		T54	20		T46	20
values[4]	3915	1			T9	2		T125	6		T101	16
values[5]	4295	1			T7	14		T13	20		T17	2
values[6]	4009	1			T8	4		T54	20		T106	20
values[7]	3998	1			T53	14		T54	40		T46	146

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4291	1			T17	2		T55	2		T54	20
values[1]	3994	1			T8	4		T51	4		T30	20
values[2]	3665	1			T7	14		T54	20		T46	64
values[3]	4090	1			T54	20		T106	20		T184	6
values[4]	4080	1			T54	20		T176	8		T259	2
values[5]	3666	1			T9	2		T53	14		T57	4
values[6]	4851	1			T56	16		T103	16		T260	2
values[7]	3907	1			T13	20		T54	60		T101	16

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31740

1

T7

14

T9

2

T13

20

auto[1]

804

1

T8

4

T54

10

T46

8

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	439	1			T105	10		T47	25		T36	20
auto[0]	values[0]	values[1]	512	1			T30	20		T86	75		T210	20
auto[0]	values[0]	values[2]	416	1			T275	14		T204	43		T248	56
auto[0]	values[0]	values[3]	570	1			T184	6		T46	48		T265	8
auto[0]	values[0]	values[4]	526	1			T39	29		T204	38		T246	14
auto[0]	values[0]	values[5]	239	1			T60	20		T224	20		T225	20
auto[0]	values[0]	values[6]	629	1			T235	6		T60	20		T201	104
auto[0]	values[0]	values[7]	442	1			T54	19		T266	6		T39	25
auto[0]	values[1]	values[0]	556	1			T60	20		T224	20		T86	41
auto[0]	values[1]	values[1]	523	1			T170	6		T60	20		T207	77
auto[0]	values[1]	values[2]	520	1			T206	29		T279	2		T300	4
auto[0]	values[1]	values[3]	348	1			T59	41		T301	6		T204	20
auto[0]	values[1]	values[4]	459	1			T259	2		T60	20		T262	16
auto[0]	values[1]	values[5]	599	1			T104	8		T86	20		T210	58
auto[0]	values[1]	values[6]	384	1			T269	10		T210	20		T302	12
auto[0]	values[1]	values[7]	446	1			T175	2		T256	18		T267	2
auto[0]	values[2]	values[0]	666	1			T210	18		T219	19		T198	26
auto[0]	values[2]	values[1]	632	1			T51	4		T37	20		T207	20
auto[0]	values[2]	values[2]	395	1			T54	19		T46	24		T210	20
auto[0]	values[2]	values[3]	360	1			T36	19		T177	17		T207	21
auto[0]	values[2]	values[4]	497	1			T280	10		T204	20		T213	19
auto[0]	values[2]	values[5]	523	1			T204	20		T219	20		T273	66
auto[0]	values[2]	values[6]	516	1			T103	16		T177	62		T207	18
auto[0]	values[2]	values[7]	459	1			T46	24		T245	6		T207	20
auto[0]	values[3]	values[0]	605	1			T55	2		T107	20		T48	27
auto[0]	values[3]	values[1]	537	1			T59	28		T177	19		T207	20
auto[0]	values[3]	values[2]	524	1			T46	19		T62	39		T268	2
auto[0]	values[3]	values[3]	863	1			T278	6		T210	19		T213	80
auto[0]	values[3]	values[4]	406	1			T36	90		T286	20		T86	24
auto[0]	values[3]	values[5]	435	1			T223	6		T226	33		T303	20
auto[0]	values[3]	values[6]	607	1			T47	19		T39	21		T213	40
auto[0]	values[3]	values[7]	324	1			T54	20		T87	62		T298	6
auto[0]	values[4]	values[0]	361	1			T227	10		T46	73		T107	19
auto[0]	values[4]	values[1]	428	1			T125	6		T86	39		T304	129
auto[0]	values[4]	values[2]	375	1			T36	20		T281	20		T305	6
auto[0]	values[4]	values[3]	494	1			T36	20		T107	20		T59	20
auto[0]	values[4]	values[4]	586	1			T210	20		T207	51		T87	21
auto[0]	values[4]	values[5]	448	1			T9	2		T57	4		T107	20
auto[0]	values[4]	values[6]	579	1			T260	2		T177	20		T207	20
auto[0]	values[4]	values[7]	553	1			T101	16		T183	6		T58	14
auto[0]	values[5]	values[0]	475	1			T17	2		T222	10		T48	22
auto[0]	values[5]	values[1]	575	1			T59	72		T60	20		T204	20
auto[0]	values[5]	values[2]	351	1			T7	14		T47	26		T306	10
auto[0]	values[5]	values[3]	420	1			T257	14		T174	29		T87	20
auto[0]	values[5]	values[4]	682	1			T54	19		T176	8		T36	32
auto[0]	values[5]	values[5]	415	1			T36	20		T248	20		T208	23
auto[0]	values[5]	values[6]	530	1			T56	16		T36	68		T59	19
auto[0]	values[5]	values[7]	735	1			T13	20		T47	85		T86	20
auto[0]	values[6]	values[0]	526	1			T210	37		T202	18		T230	18
auto[0]	values[6]	values[1]	442	1			T60	19		T48	21		T207	33
auto[0]	values[6]	values[2]	596	1			T296	2		T294	2		T210	20
auto[0]	values[6]	values[3]	358	1			T54	18		T106	20		T47	38
auto[0]	values[6]	values[4]	431	1			T46	19		T214	36		T62	20
auto[0]	values[6]	values[5]	403	1			T46	19		T60	19		T307	12
auto[0]	values[6]	values[6]	745	1			T36	33		T308	4		T87	72
auto[0]	values[6]	values[7]	369	1			T46	43		T36	20		T86	51
auto[0]	values[7]	values[0]	564	1			T54	19		T46	62		T36	35
auto[0]	values[7]	values[1]	237	1			T39	20		T204	20		T309	8
auto[0]	values[7]	values[2]	401	1			T46	20		T47	18		T61	16
auto[0]	values[7]	values[3]	559	1			T86	28		T39	28		T207	60
auto[0]	values[7]	values[4]	401	1			T200	10		T198	23		T253	49
auto[0]	values[7]	values[5]	528	1			T53	14		T167	4		T270	6
auto[0]	values[7]	values[6]	732	1			T238	18		T198	25		T242	75
auto[0]	values[7]	values[7]	484	1			T54	16		T46	62		T59	66
auto[1]	values[0]	values[0]	7	1			T237	2		T253	1		T201	1
auto[1]	values[0]	values[1]	10	1			T219	3		T239	1		T41	1
auto[1]	values[0]	values[2]	12	1			T248	5		T201	1		T41	2
auto[1]	values[0]	values[3]	12	1			T46	2		T204	3		T219	1
auto[1]	values[0]	values[4]	9	1			T195	2		T310	1		T311	1
auto[1]	values[0]	values[5]	7	1			T312	1		T313	2		T314	3
auto[1]	values[0]	values[6]	9	1			T201	4		T315	2		T316	1
auto[1]	values[0]	values[7]	13	1			T54	1		T39	3		T213	1
auto[1]	values[1]	values[0]	7	1			T86	1		T230	4		T317	2
auto[1]	values[1]	values[1]	7	1			T219	1		T239	1		T318	2
auto[1]	values[1]	values[2]	10	1			T177	3		T244	1		T236	1
auto[1]	values[1]	values[3]	8	1			T236	1		T293	3		T212	2
auto[1]	values[1]	values[4]	18	1			T236	4		T201	1		T239	3
auto[1]	values[1]	values[5]	13	1			T210	2		T230	1		T319	1
auto[1]	values[1]	values[6]	13	1			T201	2		T319	1		T320	1
auto[1]	values[1]	values[7]	20	1			T213	2		T211	8		T162	5
auto[1]	values[2]	values[0]	15	1			T210	2		T219	1		T198	1
auto[1]	values[2]	values[1]	11	1			T87	1		T219	1		T198	1
auto[1]	values[2]	values[2]	13	1			T54	1		T229	3		T211	2
auto[1]	values[2]	values[3]	16	1			T36	1		T177	3		T201	3
auto[1]	values[2]	values[4]	8	1			T213	1		T253	2		T201	1
auto[1]	values[2]	values[5]	4	1			T321	2		T322	1		T323	1
auto[1]	values[2]	values[6]	19	1			T177	4		T207	2		T219	4
auto[1]	values[2]	values[7]	5	1			T324	3		T71	2		-	-
auto[1]	values[3]	values[0]	9	1			T208	1		T146	2		T295	2
auto[1]	values[3]	values[1]	16	1			T59	1		T177	1		T196	1
auto[1]	values[3]	values[2]	10	1			T46	1		T62	1		T230	1
auto[1]	values[3]	values[3]	28	1			T210	1		T213	2		T226	2
auto[1]	values[3]	values[4]	12	1			T286	2		T86	2		T248	2
auto[1]	values[3]	values[5]	12	1			T239	2		T325	4		T326	1
auto[1]	values[3]	values[6]	9	1			T47	1		T39	1		T146	1
auto[1]	values[3]	values[7]	8	1			T87	1		T229	1		T327	1
auto[1]	values[4]	values[0]	6	1			T46	1		T107	1		T226	1
auto[1]	values[4]	values[1]	19	1			T86	2		T89	8		T236	1
auto[1]	values[4]	values[2]	1	1			T161	1		-	-		-	-
auto[1]	values[4]	values[3]	13	1			T87	3		T287	1		T161	1
auto[1]	values[4]	values[4]	12	1			T207	2		T87	1		T273	1
auto[1]	values[4]	values[5]	13	1			T86	1		T207	4		T328	2
auto[1]	values[4]	values[6]	15	1			T177	1		T236	1		T293	5
auto[1]	values[4]	values[7]	12	1			T177	2		T204	1		T253	1
auto[1]	values[5]	values[0]	18	1			T207	1		T213	1		T329	6
auto[1]	values[5]	values[1]	16	1			T59	4		T242	1		T236	1
auto[1]	values[5]	values[2]	8	1			T47	1		T177	1		T230	1
auto[1]	values[5]	values[3]	10	1			T174	3		T248	1		T253	2
auto[1]	values[5]	values[4]	19	1			T54	1		T36	2		T86	2
auto[1]	values[5]	values[5]	8	1			T248	2		T208	3		T162	1
auto[1]	values[5]	values[6]	23	1			T36	1		T59	1		T60	2
auto[1]	values[5]	values[7]	10	1			T39	1		T89	1		T330	2
auto[1]	values[6]	values[0]	22	1			T210	3		T202	2		T230	2
auto[1]	values[6]	values[1]	26	1			T8	4		T60	1		T48	3
auto[1]	values[6]	values[2]	15	1			T293	1		T230	1		T331	2
auto[1]	values[6]	values[3]	21	1			T54	2		T47	3		T86	1
auto[1]	values[6]	values[4]	9	1			T46	1		T316	1		T164	1
auto[1]	values[6]	values[5]	11	1			T46	1		T60	1		T202	2
auto[1]	values[6]	values[6]	23	1			T36	3		T87	1		T202	1
auto[1]	values[6]	values[7]	12	1			T86	1		T225	1		T273	5
auto[1]	values[7]	values[0]	15	1			T54	1		T46	2		T224	3
auto[1]	values[7]	values[1]	3	1			T39	1		T314	2		-	-
auto[1]	values[7]	values[2]	18	1			T47	2		T61	8		T281	1
auto[1]	values[7]	values[3]	10	1			T39	2		T207	1		T332	2
auto[1]	values[7]	values[4]	5	1			T281	2		T311	1		T333	1
auto[1]	values[7]	values[5]	8	1			T177	1		T230	1		T239	2
auto[1]	values[7]	values[6]	18	1			T198	3		T89	3		T202	1
auto[1]	values[7]	values[7]	15	1			T54	4		T59	4		T204	1