Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	906	1			T36	4		T37	10		T38	19
all_values[1]	906	1			T36	4		T37	10		T38	19
all_values[2]	906	1			T36	4		T37	10		T38	19
all_values[3]	906	1			T36	4		T37	10		T38	19
all_values[4]	906	1			T36	4		T37	10		T38	19
all_values[5]	906	1			T36	4		T37	10		T38	19
all_values[6]	906	1			T36	4		T37	10		T38	19
all_values[7]	906	1			T36	4		T37	10		T38	19

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3873

1

T36

17

T37

46

T38

84

auto[1]

3375

1

T36

15

T37

34

T38

68

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2955

1

T36

17

T37

25

T38

62

auto[1]

4293

1

T36

15

T37

55

T38

90

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4165

1

T36

22

T37

38

T38

93

auto[1]

3083

1

T36

10

T37

42

T38

59

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	182	1			T36	1		T37	1		T38	4
all_values[0]	auto[0]	auto[0]	auto[1]	81	1			T36	1		T38	3		T39	2
all_values[0]	auto[0]	auto[1]	auto[0]	162	1			T36	1		T38	3		T39	2
all_values[0]	auto[0]	auto[1]	auto[1]	93	1			T37	2		T38	1		T39	1
all_values[0]	auto[1]	auto[0]	auto[1]	199	1			T36	1		T37	3		T38	3
all_values[0]	auto[1]	auto[1]	auto[1]	189	1			T37	4		T38	5		T39	1
all_values[1]	auto[0]	auto[0]	auto[0]	170	1			T36	1		T37	1		T38	5
all_values[1]	auto[0]	auto[0]	auto[1]	89	1			T39	4		T160	2		T173	1
all_values[1]	auto[0]	auto[1]	auto[0]	163	1			T36	1		T38	2		T160	1
all_values[1]	auto[0]	auto[1]	auto[1]	87	1			T37	2		T38	5		T39	2
all_values[1]	auto[1]	auto[0]	auto[1]	220	1			T36	1		T37	2		T38	2
all_values[1]	auto[1]	auto[1]	auto[1]	177	1			T36	1		T37	5		T38	5
all_values[2]	auto[0]	auto[0]	auto[0]	180	1			T36	2		T37	3		T38	7
all_values[2]	auto[0]	auto[0]	auto[1]	76	1			T37	2		T38	1		T174	4
all_values[2]	auto[0]	auto[1]	auto[0]	166	1			T37	3		T160	5		T174	5
all_values[2]	auto[0]	auto[1]	auto[1]	104	1			T36	1		T38	2		T39	2
all_values[2]	auto[1]	auto[0]	auto[1]	204	1			T36	1		T37	2		T38	6
all_values[2]	auto[1]	auto[1]	auto[1]	176	1			T38	3		T39	4		T160	1
all_values[3]	auto[0]	auto[0]	auto[0]	195	1			T36	2		T37	1		T38	1
all_values[3]	auto[0]	auto[0]	auto[1]	96	1			T37	3		T38	4		T160	1
all_values[3]	auto[0]	auto[1]	auto[0]	150	1			T37	1		T38	5		T39	1
all_values[3]	auto[0]	auto[1]	auto[1]	85	1			T36	1		T38	2		T39	2
all_values[3]	auto[1]	auto[0]	auto[1]	219	1			T36	1		T37	4		T38	5
all_values[3]	auto[1]	auto[1]	auto[1]	161	1			T37	1		T38	2		T39	4
all_values[4]	auto[0]	auto[0]	auto[0]	175	1			T36	1		T37	2		T38	5
all_values[4]	auto[0]	auto[0]	auto[1]	76	1			T37	1		T39	1		T160	3
all_values[4]	auto[0]	auto[1]	auto[0]	163	1			T36	3		T37	1		T38	5
all_values[4]	auto[0]	auto[1]	auto[1]	93	1			T38	2		T39	1		T160	2
all_values[4]	auto[1]	auto[0]	auto[1]	230	1			T37	3		T38	4		T39	1
all_values[4]	auto[1]	auto[1]	auto[1]	169	1			T37	3		T38	3		T39	3
all_values[5]	auto[0]	auto[0]	auto[0]	280	1			T36	1		T37	3		T38	4
all_values[5]	auto[0]	auto[1]	auto[0]	234	1			T36	1		T37	2		T38	8
all_values[5]	auto[1]	auto[0]	auto[1]	212	1			T36	1		T37	4		T38	5
all_values[5]	auto[1]	auto[1]	auto[1]	180	1			T36	1		T37	1		T38	2
all_values[6]	auto[0]	auto[0]	auto[0]	190	1			T37	3		T38	5		T39	1
all_values[6]	auto[0]	auto[0]	auto[1]	87	1			T36	1		T37	1		T38	1
all_values[6]	auto[0]	auto[1]	auto[0]	168	1			T37	1		T38	1		T39	5
all_values[6]	auto[0]	auto[1]	auto[1]	85	1			T36	1		T38	5		T160	5
all_values[6]	auto[1]	auto[0]	auto[1]	211	1			T36	1		T37	2		T38	5
all_values[6]	auto[1]	auto[1]	auto[1]	165	1			T36	1		T37	3		T38	2
all_values[7]	auto[0]	auto[0]	auto[0]	219	1			T37	1		T38	5		T39	5
all_values[7]	auto[0]	auto[0]	auto[1]	85	1			T37	1		T38	4		T160	2
all_values[7]	auto[0]	auto[1]	auto[0]	158	1			T36	3		T37	2		T38	2
all_values[7]	auto[0]	auto[1]	auto[1]	73	1			T37	1		T38	1		T39	3
all_values[7]	auto[1]	auto[0]	auto[1]	197	1			T36	1		T37	3		T38	5
all_values[7]	auto[1]	auto[1]	auto[1]	174	1			T37	2		T38	2		T39	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal