Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1667

1

T4

1

T6

4

T10

17

auto[1]

1639

1

T6

3

T10

26

T26

4

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1726

1

T6

7

T28

11

T30

9

auto[1]

1580

1

T4

1

T10

43

T26

14

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2666

1

T4

1

T6

3

T10

43

auto[1]

640

1

T6

4

T28

4

T30

5

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	667	1			T4	1		T6	2		T10	10
valid[1]	709	1			T6	1		T10	6		T26	3
valid[2]	617	1			T6	1		T10	6		T26	1
valid[3]	662	1			T6	2		T10	12		T26	2
valid[4]	651	1			T6	1		T10	9		T26	6

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	106	1			T28	2		T32	1		T63	1
auto[0]	auto[0]	valid[0]	auto[1]	161	1			T4	1		T10	5		T26	2
auto[0]	auto[0]	valid[1]	auto[0]	116	1			T28	2		T32	1		T50	2
auto[0]	auto[0]	valid[1]	auto[1]	178	1			T10	3		T26	2		T28	1
auto[0]	auto[0]	valid[2]	auto[0]	100	1			T6	1		T63	2		T65	1
auto[0]	auto[0]	valid[2]	auto[1]	133	1			T10	2		T29	3		T33	2
auto[0]	auto[0]	valid[3]	auto[0]	109	1			T28	2		T63	1		T50	1
auto[0]	auto[0]	valid[3]	auto[1]	157	1			T10	4		T26	2		T28	2
auto[0]	auto[0]	valid[4]	auto[0]	92	1			T32	1		T50	1		T36	1
auto[0]	auto[0]	valid[4]	auto[1]	178	1			T10	3		T26	4		T28	1
auto[0]	auto[1]	valid[0]	auto[0]	132	1			T6	1		T30	1		T50	1
auto[0]	auto[1]	valid[0]	auto[1]	141	1			T10	5		T29	1		T94	2
auto[0]	auto[1]	valid[1]	auto[0]	117	1			T32	1		T63	1		T50	2
auto[0]	auto[1]	valid[1]	auto[1]	169	1			T10	3		T26	1		T29	4
auto[0]	auto[1]	valid[2]	auto[0]	109	1			T30	2		T32	4		T63	1
auto[0]	auto[1]	valid[2]	auto[1]	154	1			T10	4		T26	1		T94	2
auto[0]	auto[1]	valid[3]	auto[0]	104	1			T28	1		T30	1		T32	3
auto[0]	auto[1]	valid[3]	auto[1]	151	1			T10	8		T29	1		T33	1
auto[0]	auto[1]	valid[4]	auto[0]	101	1			T6	1		T65	1		T50	3
auto[0]	auto[1]	valid[4]	auto[1]	158	1			T10	6		T26	2		T28	1
auto[1]	auto[0]	valid[0]	auto[0]	64	1			T6	1		T28	1		T30	1
auto[1]	auto[0]	valid[1]	auto[0]	67	1			T28	1		T32	1		T50	1
auto[1]	auto[0]	valid[2]	auto[0]	67	1			T32	1		T63	2		T65	1
auto[1]	auto[0]	valid[3]	auto[0]	71	1			T6	2		T32	1		T63	1
auto[1]	auto[0]	valid[4]	auto[0]	68	1			T32	1		T65	1		T23	1
auto[1]	auto[1]	valid[0]	auto[0]	63	1			T63	3		T65	2		T346	1
auto[1]	auto[1]	valid[1]	auto[0]	62	1			T6	1		T32	1		T63	2
auto[1]	auto[1]	valid[2]	auto[0]	54	1			T28	1		T346	1		T36	1
auto[1]	auto[1]	valid[3]	auto[0]	70	1			T28	1		T30	2		T50	3
auto[1]	auto[1]	valid[4]	auto[0]	54	1			T30	2		T63	1		T65	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal